參數(shù)資料
型號(hào)： GS81302TT07E-333IT
廠(chǎng)商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 16M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 2/31頁(yè)
文件大?。?/td> 1198K
代理商： GS81302TT07E-333IT
Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table
Kn
LD
R/W
DQ
Operation
A + 0
A + 1
↑
1
X
Hi-Z / *
Deselect
↑
0
D@Kn+1
Write
↑
0
1
Q@Kn+2
Read
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “V” = input “valid”; “X” = input “don’t care”.
2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP
and Write commands, 2.0 cycles after the command is sampled.
5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.0
cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the
state of the DQ input termination. See the Input Termination Impedance Control section for more information.
Burst of 2 Byte Write Clock Truth Table
BW
Current Operation
D
K
↑
(tn + 1)
K
↑
(tn + 1)
K
↑
(tn)
K
↑
(tn +1 )
K
↑
(tn + 1)
T
Write
Dx stored if BWn = 0 in both data transfers
D1
D2
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D1
X
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D2
F
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
GS81302TT07/10/19/37E-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
10/31
2011, GSI Technology
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