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參數(shù)資料
| 型號： | GS8128418B-167IV |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 8M X 18 CACHE SRAM, 8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, FPBGA-119 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大小： | 652K |
| 代理商： | GS8128418B-167IV |
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JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
GS8128418/36B-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 7/2010
25/30
2007, GSI Technology
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS8128418B-167V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 144MBIT 8MX18 8NS/3.4NS 119FPBGA - Trays |
| GS8128418B-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 144MBIT 8MX18 7.5NS/3NS 119FPBGA - Trays |
| GS8128418B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 144MBIT 8MX18 7.5NS/3NS 119FPBGA - Trays |
| GS8128418B-200IV | 制造商:GSI Technology 功能描述:8M X 18 (144 MEG) - Trays |
| GS8128418B-200V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 144MBIT 8MX18 7.5NS/3NS 119FPBGA - Trays |
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