- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370379 > GS1561* Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. PDF資料下載
參數(shù)資料
| 型號： | GS1561* |
| 英文描述： | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. |
| 中文描述： | 時鐘重計解串器的HD - SDI的。標(biāo)清SDI |
| 文件頁數(shù)： | 47/55頁 |
| 文件大?。?/td> | 922K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
GENNUM CORPORATION
27360 - 2
47 of 55
G
Figure 13 HD PCLK to Data Timing
Figure 14 SD PCLK to Data Timing
3.11.2 Parallel Output in SMPTE Mode
When the device is operating in SMPTE mode, (see Section
3.7), both SD and HD data may be presented to the output
bus in either multiplexed or demultiplexed form depending
on the setting of the 20bit/10bit input pin.
In 20-bit mode, (20bit/10bit = HIGH), the output data will be
word aligned, demultiplexed luma and chroma data. Luma
words will always appear on DOUT[19:10] while chroma
words will occupy DOUT[9:0].
In 10-bit mode, (20bit/10bit = LOW), the output data will be
word aligned, multiplexed luma and chroma data. The data
will be presented on DOUT[19:10], and the device will force
DOUT[9:0] LOW.
3.11.3 Parallel Output in DVB-ASI Mode
When operating in DVB-ASI mode, (see Section 3.8), the
GS1560A automatically configures the output port for 10-bit
operation regardless of the setting of the 20bit/10bit pin.
The extracted 8-bit data words will be presented on
DOUT[17:10] such that DOUT17 = HOUT is the most
significant bit of the decoded transport stream data and
DOUT10 = AOUT is the least significant bit.
In addition, DOUT19 and DOUT18 will be configured as the
DVB-ASI status signals SYNCOUT and WORDERR
respectively. See Section 3.8.2 for a description of these
DVB-ASI specific output signals.
DOUT[9:0] will be forced LOW when the GS1560A is
operating in DVB-ASI mode.
3.11.4 Parallel Output in Data-Through Mode
When operating in Data-Through mode, (see Section 3.9),
the GS1560A presents data to the output data bus without
performing any decoding, descrambling or word-alignment.
As described in Section 3.9, the data bus outputs will be
forced to logic LOW if the device is set to operate in master
mode but cannot identify SMPTE TRS ID or DVB-ASI sync
words in the input data stream.
3.11.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS1560A is
determined by the output data format. Table 16 below lists
the possible output signal formats and their corresponding
parallel clock rates. Note that DVB-ASI output will always be
in 10-bit format, regardless of the setting of the 20bit/10bit
pin.
PCLK
DOUT[19:0]
DATA
Control signal
output
t
OH
t
OD
HD MODE
PCLK
DOUT[19:0]
DATA
Control signal
output
t
OH
t
OD
SD MODE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS15T48-5 | 15W DC-DC CONVERTER |
| GS15T48 | |
| GS15T5-5.2 | DC-to-DC Voltage Converter |
| GS15T5-52 | 15W DC-DC CONVERTER FOR ECL |
| GS175T48-12 | 120W/175W DC-DC CONVERTERS FAMILY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561-CF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFTE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。