參數(shù)資料
型號： GS1561*
英文描述： Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply.
中文描述： 時鐘重計解串器的HD - SDI的。標(biāo)清SDI
文件頁數(shù)： 44/55頁
文件大?。?/td> 922K
GENNUM CORPORATION
27360 - 2
44 of 55
G
3.10.6.1 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE
register is set LOW, the GS1560A will remap all codes
within the active picture between the values of 3FCh and
3FFh to 3FBh. All codes within the active picture area
between the values of 000h and 003h will be re-mapped to
004h.
In addition, 8-bit TRS and ancillary data preambles will be
remapped to 10-bit values if this feature is enabled.
3.10.6.2 EDH CRC Error Correction
The GS1560A will generate and insert active picture and full
field CRC words into the EDH data packets received by the
device. This feature is only available in SD mode and is
enabled by setting the EDH_CRC_INS bit of the
IOPROC_DISABLE register LOW.
EDH CRC calculation ranges are described in Section
3.10.5.2.
NOTE: Although the GS1560A will modify and insert EDH
CRC words and EDH packet checksums, EDH error flags
will not be updated by the device.
3.10.6.3 Ancillary Data Checksum Error Correction
When ancillary data checksum error correction and
insertion is enabled, the GS1560A will generate and insert
ancillary data checksums for all ancillary data words by
default. Where user specified ancillary data has been
programmed into the device (see Section 3.10.2.1), only the
checksums for the programmed ancillary data types will be
corrected.
This feature is enabled when the ANC_CSUM_INS bit of the
IOPROC_DISABLE register is set LOW.
3.10.6.4 Line Based CRC Correction
The GS1560A will generate and insert line based CRC
words into both the Y and C channels of the data stream.
This feature is only available in HD mode and is enabled by
setting the CRC_INS bit of the IOPROC_DISABLE register
LOW.
TABLE 14 HOST INTERFACE DESCRIPTION FOR INTERNAL PROCESSING DISABLE REGISTER
REGISTER NAME
BIT
BIT NAME
DESCRIPTION
R/W
DEFAULT
IOPROC_DISABLE
Address: 000h
15-9
Not Used
8
H_CONFIG
Horizontal sync timing output configuration. Set LOW for
active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS words. See Figure
8.
0
7
Not Used
6
Not Used
5
ILLEGAL_REMAP
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
R/W
0
4
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction insertion. In SD mode set
HIGH to disable. The IOPROC_EN/DIS pin must be set
HIGH.
R/W
0
3
ANC_CSUM_INS
Ancillary Data Check-sum insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
2
CRC_INS
Y and C line based CRC insertion. In HD mode, inserts
line based CRC words in both the Y and C channels.
Set HIGH to disable. The IOPROC_EN/DIS pin must be
set HIGH.
R/W
0
1
LNUM_INS
Y and C line number insertion. In HD mode set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1561-CF 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
GS1561-CFT 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFTE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
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