參數(shù)資料
型號: GS1561*
英文描述: Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply.
中文描述: 時鐘重計解串器的HD - SDI的。標清SDI
文件頁數(shù): 33/55頁
文件大小: 922K
GENNUM CORPORATION
27360 - 2
33 of 55
G
3.10 ADDITIONAL PROCESSING FUNCTIONS
The GS1560A contains an additional data processing block
which is available in SMPTE mode only, (see Section 3.7).
3.10.1 FIFO Load Pulse
To aid in the application-specific implementation of auto-
phasing and line synchronization functions, the GS1560A
will generate a FIFO load pulse to reset line-based FIFO
storage.
The FIFO_LD output pin will normally be HIGH but will go
LOW for one PCLK period, thereby generating a FIFO write
reset signal.
The FIFO load pulse will be generated such that it is co-
timed to the SAV XYZ code word presented to the output
data bus. This ensures that the next PCLK cycle will
correspond to the first active sample of the video line.
Figure 11 shows the timing relationship between the
FIFO_LD signal and the output video data.
Figure 11
FIFO_LD
Pulse Timing
PCLK
LUMA DATA OUT
CHROMA DATA OUT
FIFO_LD
3FF
3FF
3FF
3FF
000
000
000
000
XYZ
(SAV)
000
000
000
000
XYZ
(SAV)
XYZ
(SAV)
XYZ
(SAV)
MULTIPLEXED
Y/Cr/Cb DATA OUT
PCLK
FIFO_LD
FIFO LOAD PULSE - HD 10BIT OUTPUT MODE
FIFO LOAD PULSE - HD 20BIT OUTPUT MODE
3FF
3FF
000
000
000
000
XYZ
(SAV)
MULTIPLEXED
Y/Cr/Cb DATA OUT
PCLK
PCLK
LUMA DATA OUT
CHROMA DATA OUT
FIFO_LD
FIFO_LD
XYZ
(SAV)
FIFO LOAD PULSE - SD 10BIT OUTPUT MODE
FIFO LOAD PULSE - SD 20BIT OUTPUT MODE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1561-CF 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
GS1561-CFT 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFTE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru