- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370379 > GS1561* Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. PDF資料下載
參數(shù)資料
| 型號： | GS1561* |
| 英文描述： | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. |
| 中文描述： | 時鐘重計解串器的HD - SDI的。標(biāo)清SDI |
| 文件頁數(shù)： | 26/55頁 |
| 文件大?。?/td> | 922K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
GENNUM CORPORATION
27360 - 2
26 of 55
G
When reclocker lock as indicated by the internal pll_lock
signal is achieved in this mode, one of the following will
occur:
1. In slave mode, data will be passed directly to the
parallel outputs without any further processing taking
place and the LOCKED signal will be asserted HIGH if
and only if the SMPTE_BYPASS and DVB_ASI input pins
are set LOW; or
2. In master mode, the LOCKED signal will be asserted
LOW, the parallel outputs will be latched to logic LOW,
and the SMPTE_BYPASS and DVB_ASI output signals
will also be set LOW.
3.6.2 Master Mode
Recall that the GS1560A is said to be in master mode when
the MASTER/SLAVE input signal is set HIGH. In this case,
the following four device pins become output status signals:
SMPTE_BYPASS
DVB_ASI
SD/HD
RC_BYP
The combined setting of these four pins will indicate
whether the device has locked to valid SMPTE or DVB-ASI
data at SD or HD rates. Table 2 shows the possible
combinations.
3.6.3 Slave Mode
The GS1560A is said to be in slave mode when the
MASTER/SLAVE input signal is set LOW. In this case, the
four device pins listed in Section 3.6.2 become input control
signals.
It is required that the application layer set the first three
inputs to reflect the appropriate input data format
(SMPTE_BYPASS, DVB_ASI, and SD/HD). If just one of
these three is configured incorrectly, the device will not lock
to the input data stream, and the DATA_ERROR pin will be
set LOW.
The fourth input signal, RC_BYP, allows the application
layer to determine whether the serial digital loop-through
output will be a reclocked or buffered version of the input,
(see Section 3.4.2). Table 3 shows the required settings for
various input formats.
TABLE 2 MASTER MODE OUTPUT STATUS SIGNALS
FORMAT
PIN SETTINGS
SMPTE_BYPASS
DVB_ASI
SD/HD
RC_BYP
HD SMPTE
HIGH
LOW
LOW
HIGH
SD SMPTE
HIGH
LOW
HIGH
HIGH
DVB-ASI
LOW
HIGH
HIGH
HIGH
NOT SMPTE OR DVB-ASI*
LOW
LOW
HIGH OR LOW
LOW
*NOTE: When the device locks to the data stream in PLL lock mode, the parallel outputs will be latched LOW, and
the serial loop-through output will be a buffered version of the input.
TABLE 3 SLAVE MODE INPUT CONTROL SIGNALS
FORMAT
PIN SETTINGS
SMPTE_BYPASS
DVB_ASI
SD/HD
HD SMPTE
HIGH
LOW
LOW
SD SMPTE
HIGH
LOW
HIGH
DVB-ASI
LOW
HIGH
HIGH
NOT SMPTE OR DVB-ASI*
LOW
LOW
HIGH OR LOW
*NOTE: See Section 3.9 for a complete description of Data-Through mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS15T48-5 | 15W DC-DC CONVERTER |
| GS15T48 | |
| GS15T5-5.2 | DC-to-DC Voltage Converter |
| GS15T5-52 | 15W DC-DC CONVERTER FOR ECL |
| GS175T48-12 | 120W/175W DC-DC CONVERTERS FAMILY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561-CF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFTE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。