參數(shù)資料
型號: GMM7654287CTG-5
英文描述: x64 EDO Page Mode DRAM Module
中文描述: X64的EDO公司頁面模式內存模塊
文件頁數(shù): 7/29頁
文件大?。?/td> 425K
代理商: GMM7654287CTG-5
LG Semicon
GMM7654287CTG
Capacitance
(V
CC
= 3.3V+/-0.3V, T
A
= 25C, f = 1MHz)
Symbol
C
I1
C
I2
C
13
C
14
C
I/O
Parameter
Note
1
1, 2
1, 2
1, 2
1, 2
Unit
pF
pF
pF
pF
pF
Max
30
30
30
15
17
Min
-
-
-
-
-
Input Capacitance (A0~A11)
Input Capacitance (WE0,OE0)
Input Capacitance (RAS0)
Input Capacitance (CAS0~CAS7)
I/O Capacitance (DQ0~DQ63)
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = V
IH
to disable D
OUT
.
AC Characteristics
(V
CC
= 3.3V+/-0.3V, T
A
= 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns Output timing reference levels : V
OL
/V
OH
= 0.8/2.0V
Input level : V
IL
/V
IH
= 0.0/3.0V Output load : 1 TTL gate+C
L
(100pF)
Input timing reference levels : V
IL
/V
IH
= 0.8/2.0V (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Max
Max
Min
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
4
t
RAD
3
t
RSH
t
CSH
t
CRP
Min
84
30
50
8
0
8
0
8
12
10
13
35
5
-
-
10000
-
-
-
-
37
25
-
-
-
Unit Notes
§à
§à
§à
§à
§à
§à
§à
§à
§à
§à
§à
§à
§à
t
T
t
REF
Refresh Period ( 4096 Cycles)
2
-
50
128
§à
ms
t
ODD
t
DZO
t
DZC
13
0
0
-
-
-
§à
§à
§à
60
10
104
-
40
-
10000
0
-
10
-
0
-
10
-
14
45
12
30
15
-
40
-
5
-
15
-
0
-
0
-
2
50
-
128
t
CP
8
-
§à
10
-
10000
10000
GMM7654287CTG-5
GMM7654287CTG-6
Parameter
Random Read or Write Cycle Time
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
TransitionTime
(Rise and Fall)
OE to D
IN
Delay Time
OE Delay Time from D
IN
CAS Set-up Time from D
IN
CAS Precharge Time
5
6
6
7
21
21
24
22
7
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