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參數(shù)資料
| 型號： | GMM7654287CTG-5 |
| 英文描述： | x64 EDO Page Mode DRAM Module |
| 中文描述： | X64的EDO公司頁面模式內存模塊 |
| 文件頁數(shù)： | 12/29頁 |
| 文件大?。?/td> | 425K |
| 代理商： | GMM7654287CTG-5 |
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LG Semicon
GMM7654287CTG
t
CWL,
t
DH,
t
DS
and t
CHS
should be satisfied by the both UCAS and LCAS.
t
CP
is determined by the time that both UCAS and LCAS are high.
t
HPC
(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t
HPC
(t
CAS
+ t
CP
+ 2t
T
) becomes greater than the
specified t
HPC
(min) value. The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t
OHR
and t
OH
, and between t
OFR
and t
OFF
.
t
DOH
defines the time at which the output level go cross. V
OL
=0.8V, V
OH
=2.4V of output timing
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within
64
§
period on the condition a and b below.
a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 28.
For L_version, it is available to apply each 128
§
and 31.2us instead of 64
§
and 15.6us at note
28.
At t
RASS
￡
100 us , self refresh mode is activated, and not activated at t
RASS
￡
10us. It is undefined
within the range of 10 us
￡
t
RASS
￡
100 us . for t
RASS
￡
10 us , it is necessary to satisfy t
RPS
.
XXX: H or L ( H : V
IH
(min)
V
IN
V
IH
(max), L: V
IH
(min)
V
IN
V
IH
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH
or V
IL.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
12
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