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參數(shù)資料
| 型號： | GMM7654287CTG-5 |
| 英文描述： | x64 EDO Page Mode DRAM Module |
| 中文描述： | X64的EDO公司頁面模式內(nèi)存模塊 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 425K |
| 代理商： | GMM7654287CTG-5 |
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LG Semicon
Notes:
AC measurements assume t
T
= 2
§à
.
AC initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is specified as a
reference point only: if t
RCD
is greater than the specified t
RCD
(max) limit, then access time is
controlled exclusively by t
CAC
.
Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is specified as a
reference point only: if t
RAD
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
Either t
ODD
or t
CDD
must be satisfied.
Either t
DZO
or t
DZC
must be satisfied.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between V
IH
(min) and V
IL
(max).
Assumes that t
RCD
t
RCD
(max) and t
RAD
t
RAD
(max). If t
RCD
or t
RAD
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
Assumes that t
RCD
>=t
RCD
(max) and t
RCD
+
t
CAC
(max) >=t
RAD
+
t
AA
(max).
Assumes that t
RAD
>=t
RAD
(max) and t
RCD
+
t
CAC
(max)
t
RAD
+
t
AA
(max).
Either t
RCH
or t
RRH
must be satisfied for a read cycles.
t
OFF
(max),
t
OEZ(
max), t
OFR
(max) and t
WEZ
(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
t
WCS
, t
RWD
, t
CWD,
t
AWD,
and t
CPW
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if t
WCS
>=t
WCS
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
t
RWD
>=t
RWD
(min), t
CWD
>=t
CWD
(min), t
AWD
>=t
AWD
(min) and t
CPW
>=t
CPW
(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
t
DS
and t
DH
are referred to UCAS and LCAS leading edge in early write cycles and to WE
leading edge in delayed write or read-modify-write cycles.
t
RASP
defines RAS pulse width in extended data out mode cycles.
Access time is determined by the longest among t
AA,
t
CAC
and t
ACP
.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
When both UCAS and LCAS go low at the same time, all 16-bit data are written into the
device. UCAS and LCAS cannot be staggered within the same write/read cycles.
t
ASC,
t
CAH,
t
RCS,
t
WCS,
t
WCH,
t
CSR
and t
RPC
are determined by the earlier falling edge of UCAS or
LCAS.
t
CRP,
t
CHR,
t
RCH,
t
ACP
and t
CPW
are determined by the later rising edge of UCAS or LCAS.
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