參數(shù)資料
型號(hào): GLT5640L32-5.5
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Synchronous DRAM 2M x 32 SDRAM
中文描述: 200萬的CMOS同步DRAM × 32內(nèi)存
文件頁數(shù): 22/72頁
文件大?。?/td> 2315K
代理商: GLT5640L32-5.5
G-LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-27968078
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9. Read / Write Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the
CAS
latency, even if the previous read
operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Read A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Write A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Write B
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