參數資料
型號: GLT5640L32-5.5
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Synchronous DRAM 2M x 32 SDRAM
中文描述: 200萬的CMOS同步DRAM × 32內存
文件頁數: 19/72頁
文件大?。?/td> 2315K
代理商: GLT5640L32-5.5
G-LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-27968078
- 19 -
7.Precharge
The precharge command can be asserted anytime after t
RAS(min.)
is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the
idle state after t
RP(min.)
is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL” must be satisfied. The tDPL(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid.
In the following table, minus means clocks before the reference; plus means time after the reference.
CAS
latency
2
3
Read
Write
-1
-2
+ t
DPL
(min.)
+
tDPL
(min.)
Burst lengh=4
T7
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
(t
R AS
is satisfied)
Hi - Z
Q0
Q3
Q2
Q1
PRE
Q0
Q3
Q2
Q1
Read
Read
T0
T1
T2
T3
T4
T5
T6
PRE
Hi - Z
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