參數(shù)資料
型號(hào)： GLT5640AL16P-8TC
廠商： Electronic Theatre Controls, Inc.
英文描述： INSULATION SLEEVING, 1/4" ID, PER MIL-I-23053
中文描述： 4米× 16個(gè)CMOS同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 13/72頁(yè)
文件大?。?/td> 2315K
代理商： GLT5640AL16P-8TC
G-LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-27968078
- 13 -
Current state
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
RAS
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
L
L
X
H
H
H
L
CAS
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
X
H
H
L
X
WE
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
X
Address
Command
Action
Notes
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
X
X
X
X
X
X
X
X
X
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL/
REF/SELF/MRS
Nop
→
Enter row active after tDPL
Nop
→
Enter row active after tDPL
Nop
→
Enter row active after tDPL
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
→
Enter precharge after tDPL
Nop
→
Enter precharge after tDPL
Nop
→
Enter precharge after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
→
Enter idle after tRC
Nop
→
Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
→
Enter idle after 2 Clocks
Nop
→
Enter idle after 2 Clocks
ILLEGAL
ILLEGAL
ILLEGAL
8
3
3
Write recovering
3,8,11
3,11
3,11
3
Write recovering
with auto
precharge
Auto Refreshing
Mode register
setting
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled.
5. Illegal if t
RCD
is not satisfied.
6. Illegal if t
RAS
is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy t
DPL
.
10. Illegal if t
RRD
is not satisfied.
11. Illegal for single bank, bur legal for other banks in multi-bank devices.
相關(guān)PDF資料
PDF描述
GLT5640L32 CMOS Synchronous DRAM 2M x 32 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GLT5640L32 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM
GLT5640L32-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM
GLT5640L32-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM
GLT5640L32-5.5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM
GLT5640L32-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM
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