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參數(shù)資料
| 型號： | FW322 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機控制器接口 |
| 文件頁數(shù)： | 7/148頁 |
| 文件大?。?/td> | 1723K |
| 代理商： | FW322 |
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Lucent Technologies Inc.
7
Data Sheet, Rev. 1
February 2001
FW322
1394A PCI PHY/Link Open Host Controller Interface
FW322 Functional Overview
I
PCI:
—
Revision 2.2 compliant
—
33 MHz/32-bit operation
—
Programmable burst size for PCI data transfer
—
Supports PCI Bus Power Management Interface specification v.1.1
—
Supports clockrun protocol per PCI Mobile Design Guide
—
Global byte swap function
Other Features
I
I
2
C serial ROM interface
I
CMOS process
I
3.3 V operation, 5 V tolerant inputs
I
120-pin TQFP package
The FW322 is the Lucent Technologies Microelectronics Group implementation of a high-performance, PCI bus-
based open host controller for implementation of
IEEE
1394a-2000 compliant systems and devices. Link-layer func-
tions are handled by the FW322, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-
performance and cost-effective solution for connecting and servicing multiple
IEEE
1394 (both 1394-1995 and
1394a-2000) peripheral devices can be realized.
5-6250 (F)f
Figure 1. FW322 Functional Block Diagram
PCI
BUS
PCI
CORE
ROM
OHCI
ISOCH
OHCI
ASYNC
LINK
CORE
I/F
CABLE PORT 1
PHY
CORE
CABLE PORT 0
FW322 Functional Description
The FW322 is comprised of five major functional sec-
tions (see Figure 1): PCI core, isochronous data trans-
fer, asynchronous data transfer, link core, and PHY
core. The following is a general description of each of
the five major sections.
PCI Core
The PCI core serves as the interface to the PCI bus. It
contains the state machines that allow the FW322 to
respond properly when it is the target of the transaction.
During 1394 packet transmission or reception, the PCI
core arbitrates for the PCI bus and enables the FW322
to become the bus master for reading the different
buffer descriptors and management of the actual data
transfers to/from host system memory.
The PCI core also supports the PCI Bus Power
Management Interface specification v.1.1. Included in
this support is a standard power management register
interface accessible through the PCI configuration
space. Through this register interface, software is able
to transition the FW322 into four distinct power
consumption states (D0, D1, D2, and D3). This permits
software to selectively increase/decrease the power
consumption of the FW322 for reasons such as periods
of system inactivity or power conservation. In addition,
the FW322 also includes support for hardware wake-up
mechanisms through power management events
(PMEs). When the FW322 is in a low-power state,
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