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參數(shù)資料
| 型號： | FW322 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機控制器接口 |
| 文件頁數(shù)： | 137/148頁 |
| 文件大?。?/td> | 1723K |
| 代理商： | FW322 |
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Lucent Technologies Inc.
137
Data Sheet, Rev. 1
February 2001
FW322
1394A PCI PHY/Link Open Host Controller Interface
Crystal Selection Considerations
The FW322 is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to pro-
vide the reference for an internal oscillator circuit.
IEEE
1394a-2000 standard requires that FW322 have less than
±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this, it is
recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used.
The total frequency variation must be kept below
±
100 ppm from nominal with some allowance for error introduced
by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the
total frequency variation is less than
±
100 ppm.
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (C
L
) is a function of not only the discrete load capacitors, but also
capacitances from the FW322 board traces and capacitances of the other FW322 connected components. The val-
ues for load capacitors (C
A
and C
B
) should be calculated using this formula:
C
A
= C
B
= (C
L
–
C
stray
)
×
2
Where:
C
L
= load capacitance specified by the crystal manufacturer.
C
stray
= capacitance of the board and the FW322, typically 2 pF
—
3 pF.
Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW322 PLL. The crystal and two load capacitors should be considered as a unit during
layout. They should be placed as close as possible to one another, while minimizing the loop area created by the
combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that
flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possi-
ble to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO sig-
nals.
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| FW323 | 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface |
| FW32305 | 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface |
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