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參數(shù)資料
| 型號： | FS6377-01G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
FS6377
3.2 Post Divider Muxes
As shown in Figure 2, an input mux in front of each post divider stage can select from any one of the PLL frequencies or the reference
frequency. The frequency selection is done via the I
2C-bus.
The input frequency on two of the four muxes (mux C and D in Figure 2) can be changed without reprogramming by a logic-level input
on the SEL_CD pin.
3.3 Post Dividers
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to
the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
where NF, NR and NP are the feedback, reference and post divider moduli respectively, and fCLK and fREF are the output and reference
oscillator frequencies. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications
where frequencies must be achieved exactly.
The modulus on two of the four post dividers muxes (post dividers C and D in Figure 2) can be altered without reprogramming by a
logic level on the SEL_CD pin.
4.0 Device Operation
The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur,
the registers must be loaded in a most significant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is
shown in Table 3, and I
2C-bus programming information is detailed in Section 5.0.
Control of the reference, feedback and post dividers is detailed in Table 5. Selection of these dividers directly controls how fast the VCO
will run. The maximum VCO speed is noted in
Table 13.
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram
the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the
SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-
divider(s) is/are altered.
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective power-down control bits
enabled. Note that the PD pin has an internal pull-up.
When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered down
the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up.
Rev. 4 | Page 5 of 24 | www.onsemi.com
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| FS6377-01IG-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6377-01IG-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG 3-PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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