參數(shù)資料
型號： FS6377-01G-XTP
廠商： ON Semiconductor
文件頁數(shù)： 10/24頁
文件大?。?/td> 0K
描述： IC CLOCK GEN PLL PROG 16SOIC
標準包裝： 3,000
類型： PLL 時鐘發(fā)生器
PLL： 是
輸入： 晶體
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 無/無
頻率 - 最大： 230MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
FS6377
Table 13: AC Timing Specifications
Parameter
Symbol
Conditions/Descriptions
Clock
(MHz)
Min.
Typ.
Max.
Units
Overall
Output frequency*
fO
VDD = 5.5V
VDD = 3.6V
0.8
150
100
MHz
VCO frequency*
fVCO
VDD = 5.5V
VDD = 3.6V
40
230
170
MHz
VCO gain*
AVCO
400
MHz/V
Loop filter time constant*
LFTC bit = 0
LFTC bit = 1
7
20
s
Rise time*
tr
VO = 0.5V to 4.5V; CL = 15pF
VO = 0.3V to 3.0V; CL = 15pF
1.9
1.6
ns
Fall time*
tr
VO = 4.5V to 0.5V; CL = 15pF
VO = 3.0V to 0.3V; CL = 15pF
1.8
1.5
ns
Tristate enable delay*
tPZL, tPZH
1
8
ns
Tristate disable delay*
tPZL, tPZH
1
8
ns
Clock stabilization time*
tSTB
Output active from power-up, via PD pin
After last register is written
100
1
s
ms
Divider Modulus
Feedback divider
NF
See Table 2
8
2047
Reference divider
NR
1
255
Post divider
NP
See Table 8
1
50
Clock Outputs (PLL A clock via CLK_A pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
100
45
55
%
Jitter, long term (
σy(τ))*
tj(LT)
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
100
50
45
165
ps
Jitter, period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
100
50
110
390
ps
Clock Outputs (PLL B clock via CLK_B pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
100
45
55
%
Jitter, long term (
σy(τ))*
tj(LT)
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
100
60
45
75
ps
Jitter, period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
100
60
120
400
ps
Rev. 4 | Page 18 of 24 | www.onsemi.com
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