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參數(shù)資料
| 型號(hào)： | FS6377-01G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
FS6377
6.0 Programming Information
Table 3: Register Map
Address
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Byte 15
MUX_D2[1:0]
(selected via SEL_CD = 1
MUX_C2[1:0]
(selected via SEL_CD = 1)
PDPOST_D
PDPOST_C PDPOST_B
PDPOST_A
Byte 14
POST_D2[3:0]
(selected via SEL_CD = 1)
POST_C2[3:0]
(selected via SEL_CD = 1)
Byte 13
POST_D1[3:0]
(selected via SEL_CD = 0)
POST_C1[3:0]
(selected via SEL_CD = 0)
Byte 12
POST_B[3:0]
POST_A[3:0]
Byte 11
MUX_D1[1:0]
(selected via SEL_CD = 0)
Reserved (0)
LFTC_C2
(SEL_CD = 1)
CP_C2
(SEL_CD = 1)
FBKDIV_D2[10:8] M-Counter
(selected via SEL_CD pin = 1)
Byte 10
FBKDIV_C2[7:3] M-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C2[2:0] A-Counter
(selected via SEL_CD pin = 1)
Byte 9
REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
Byte 8
MUX_C1[1:0]
(selected via SEL_CD = 0)
PDPLL_C
LFTC_C1
(SEL_CD = 0)
CP_C1
(SEL_CD = 0)
FBKDIV_c1[10:8] M-Counter
(selected via SEL_CD = 0)
Byte 7
FBKDIV_C1[7:3] M-Counter
(selected via SEL_CD = 0)
FBKDIV_C1[2:0] A-Counter
(selected via SEL_CD = 1)
Byte 6
REFDIV_C1[7:0]
(selected via SEL_CD = 0)
Byte 5
MUX_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
Byte 4
FBKDIV_B[7:3] M-Counter
FBKDIV_B[2:0] A-Counter
Byte 3
REFDIV_B[7:0]
Byte 2
MUX_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[10:8] M-Counter
Byte 1
FBKDIV_A[7:3] M-Counter
FBKDIV_A[2:0] A-Counter
Byte 0
REFDIV_A[7:0]
Note:
All register bits are cleared to zero on power-up.
6.1 Control Bit Assignment
If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output
frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time
constant.
However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.
Rev. 4 | Page 10 of 24 | www.onsemi.com
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