- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370213 > FMS9875KGC140 Integrated Photo Flash Charger and IGBT Driver 16-QFN -35 to 85 PDF資料下載
參數(shù)資料
| 型號： | FMS9875KGC140 |
| 英文描述： | Integrated Photo Flash Charger and IGBT Driver 16-QFN -35 to 85 |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 481K |
| 代理商： | FMS9875KGC140 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
PRODUCT SPECIFICATION
FMS9875
10
REV. 1.2.15 1/14/02
Analog Inputs
Input signal range is 500 to 1000mV to support conversion of
single-ended signals with a typical amplitude of 700mV p-p.
With the clamp active, each input can accommodate compos-
ite sync, a negative 300mV excursion.
Inputs are optimized for a source resistance of 37.5 to 75
.
To reduce noise sensitivity, the 400MHz input bandwidth
may be reduced by adding a small series inductor prior to the
75
terminating resistor. See Applications Section.
Clamps
If the incoming signals are not ground referenced, a clamp
must be used to establish the incoming video range. Prior to
each A/D converter, each channel includes a clamp that
allows capacitively coupled input levels to be matched to the
A/D converter reference level when the clamp pulse is active.
Source of the clamp timing is determined by the XCLAMP
register bit.
Clamping levels depend upon the incoming signal format:
1.
RGB
. All signals must be clamped to the A/D converter
lower reference voltage, which is ground.
2.
YP
B
P
R
. The Y signal must be clamped to ground.
P
B
P
R
signals must be clamped to the mid-level of the
A/D converter range, to establish the zero level of the
signed P
B
P
R
signals.
With 700 mV incoming signal levels, nominal clamp levels
are 0 mV for ground and 350 mV for mid-level. Offset and
gain control can be used to trim input levels to match the
clamp voltages.
Clamps levels can be derived from either of two sources:
1.
Internal Voltages:
a) Y and GBR signals are clamped to the A/D converter
lower reference voltage that can be adjusted by the
Offset register value.
b) PBPR signals are clamped to the A/D mid-scale v
oltage, which cannot be adjusted by the Offset
control. Instead, the data output is forced to code
128 during the clamping period.
Clamp Control Register bits should be set as follows:
Table 3. Internal Clamp Setup
2.
External voltages levels connected to the GY
REF
, BP
REF
and RP
REF
inputs. Nominal values are 0 mV for Y and
350 mV for P
B
and P
R
. Clamp Control Register bits
should be set as follows:
Table 4. External Clamp Setup
External clamp levels should be established to match the
incoming signals. For example, with 650 mV peak-to-peak
P
B
P
R
signals, the mid-point should be set to 325 mV.
Internal clamp timing is generated by the Timing and
Control Block. Position and width of the internal clamp
pulse, ICLAMP are programmable through registers CD and
CW. External clamp input is selected by register bit
XCLAMP and the external clamp polarity selected through
register bit XCLAMPOL. To disable the clamp for DC
coupled inputs, set XCLAMP = 1 with either of these
conditions:
1.
XCLAMPOL = 0 with input CLAMP = H.
2.
XCLAMPOL = 1 with input CLAMP = L.
Best performance will be achieved with the clamp set active
for most of the black signal level interval between the trailing
edge of horizontal sync and the start of active video. Insufficient
clamping can cause brightness changes at the top of the image
and slow recovery from large changes in Average Picture
Level (APL). Recommended clamp delay value, CD is 0x10
to 0x20 for most standard video sources.
Analog-to-Digital Converter
Figure 2 is a block diagram of the ADC core with gain and
offset functions. G
7-0
, OS
5-0
, V
IN
and D
7-0
generically refer
to the gain and offset register values, analog input and paral-
lel data output of any RGB channel.
GYLEVEL
00
00
BPLEVEL
00
10
RPLEVEL
00
10
GBR
YP
B
P
R
GYLEVEL
01
BPLEVEL
01
RPLEVEL
01
GBR
YP
B
P
R
相關PDF資料 |
PDF描述 |
|---|---|
| FMS9875KGC140X | |
| FMS988AKAC100 | Signal Conditioner |
| FMS988AKAC140 | Signal Conditioner |
| FMU1 | TRANSISTOR | SOT-143R |
| RU101K | TRANSISTOR | SOT-23 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FMS9875KGC140X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| FMS9875KWC | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| FMS9884A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps |
| FMS9884AKAC100 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 MQFP RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| FMS9884AKAC140 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 MQFP RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。