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參數(shù)資料
| 型號： | FMS9875KGC100 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 517K |
| 代理商： | FMS9875KGC100 |
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FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
11
Within the A/D converter core are the following elements:
1.
Differential track and hold.
2.
Differential analog-to-digital converter.
Setting the gain register value G7-0 (GRP7-0, GGY7-0, GBP7-0),
establishes the gain D/A converter voltage which is the upper
A/D reference voltage. Increasing the gain register value
reduces the output level. Conversion range is dened by the gain
setting according to Table 5.
Table 5. Gain Calibration
A/D Converter sensitivity is:
Offset is set through the Track and Hold, which translates the
ground referenced input to a differential voltage centered
around A/D common mode bias voltage.
The 6-bit Offset D/A converter injects a current into RLEVEL
with two components:
1.
IBIAS to establish the A/D common mode voltage.
2.
IOFFSET to set the offset from the common mode level.
Voltage offset from the common mode voltage at the invert-
ing input of the Track and Hold is:
D/A converter gain tracks A/D gain with 1 LSB of offset
corresponding to 1LSB of gain. Increasing the offset of a
video signal increases brightness of the picture. Data output
from the A/D converter is:
Impact of the offset values OSGY5-0, OSBP5-0, and OSRP5-0
is shown in Table 6.
Table 6. Offset Calibration
Sampling Clock PHASE Adjustment
Bandwidth of TV video is typically well below the horizon-
tal sampling rate. Consequently, PHASE has little impact on
images sampled in the YPBPR format or RGB signals derived
from a video source. By contrast, PC-generated image
quality is strongly impacted by the PHASE4-0 value. If
PHASE is not set correctly, any section of an image
consisting of vertical lines may exhibit tearing.
Figure 3 shows how an analog input, VIN is sampled by the
rising edge of SCK after a delay PHASE from the rising
edge of either PXCK or XCK. SCK can be delayed up to 32
steps in 11.25° increments by adjusting the register value,
PHASE4-0.
G7-0
Conversion Range (mV)
0
500
102
700
255
1000
S
255
500
---------
=
255
G
70
–
+
-----------------------------LSB mV
OS5-0
Equivalent Offset (bits)
0
-31d
31
0
63
32d
V
OS
50
–
31
–
()
255
G
70
–
+
255
-----------------------------
500
255
---------
=
D
70
–
SV
IN
OS
50
–
31
–
()
–
=
Figure 2. A/D Converter Architecture
A/D
D7-0
VIN
+
-
D/A
Current
D/A
Gain
Register
Offset
Register
RLEVEL
SCK
IBIAS + IOFFSET
VREF
G7-0
OS5-0
Track &
Hold
A/D Core
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