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參數(shù)資料
| 型號(hào)： | FMS9875KGC100 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 517K |
| 代理商： | FMS9875KGC100 |
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FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
3
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock sig-
nal, PXCK that is fed to the Timing and Control logic. Fre-
quency of PXCK is set by the register programmable PLL
divide ratio, PLLN.
COAST is an input that disables the PLL lock to the horizon-
tal sync input, HSIN. If HSIN is to be disregarded for a
period such as the vertical sync interval, COAST allows the
VCO frequency to be maintained. Missing horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I2C/SMBus compatible
serial port. Four serial addresses are pin selectable.
Pin Assignments
100-Lead MQFP (KG)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DYG (7)
DYG (6)
DYG (5)
DYG (4)
DYG (3)
DYG (2)
DYG (1)
DYG (0)
GND
VDDO
DCK
HSOUT
DCSOUT
GND
VDDO
GND
VDDA
PWRDNB
REFOUT
REFIN
VDDA
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDDO
GND
NC
GND
VDDP
GND
VDDP
GND
LPF
XCK
VDDP
GND
COAST
HSIN
GND
VDDP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDO
GND
DPB
(0)
DPB
(1)
DPB
(2)
DPB
(3)
DPB
(4)
DPB
(5)
DPB
(6)
DPB
(7)
VDDO
GND
VDDO
GND
DPR
(0)
DPR
(1)
DPR
(2)
DPR
(3)
DPR
(4)
DPR
(5)
DPR
(6)
DPR
(7)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
ASCIN
YGIN
YGREF
VDDA
GND
VDDA
GND
BPIN
BPREF
VDDA
GND
VDDA
GND
RPIN
RPREF
VDDA
GND
VDDA
INVSCK
CLAMP
SDA
SCL
A0
A1
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