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參數(shù)資料
| 型號： | FMS9875KGC100 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 2/31頁 |
| 文件大?。?/td> | 517K |
| 代理商： | FMS9875KGC100 |
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PRODUCT SPECIFICATION
FMS9875
10
REV. 1.2.15 1/14/02
Analog Inputs
Input signal range is 500 to 1000mV to support conversion of
single-ended signals with a typical amplitude of 700mV p-p.
With the clamp active, each input can accommodate compos-
ite sync, a negative 300mV excursion.
Inputs are optimized for a source resistance of 37.5 to 75
.
To reduce noise sensitivity, the 400MHz input bandwidth
may be reduced by adding a small series inductor prior to the
75
terminating resistor. See Applications Section.
Clamps
If the incoming signals are not ground referenced, a clamp
must be used to establish the incoming video range. Prior to
each A/D converter, each channel includes a clamp that
allows capacitively coupled input levels to be matched to the
A/D converter reference level when the clamp pulse is active.
Source of the clamp timing is determined by the XCLAMP
register bit.
Clamping levels depend upon the incoming signal format:
1.
RGB. All signals must be clamped to the A/D converter
lower reference voltage, which is ground.
2.
YPBPR. The Y signal must be clamped to ground.
PBPR signals must be clamped to the mid-level of the
A/D converter range, to establish the zero level of the
signed PBPR signals.
With 700 mV incoming signal levels, nominal clamp levels
are 0 mV for ground and 350 mV for mid-level. Offset and
gain control can be used to trim input levels to match the
clamp voltages.
Clamps levels can be derived from either of two sources:
1.
Internal Voltages:
a) Y and GBR signals are clamped to the A/D converter
lower reference voltage that can be adjusted by the
Offset register value.
b) PBPR signals are clamped to the A/D mid-scale v
oltage, which cannot be adjusted by the Offset
control. Instead, the data output is forced to code
128 during the clamping period.
Clamp Control Register bits should be set as follows:
Table 3. Internal Clamp Setup
2.
External voltages levels connected to the GYREF, BPREF
and RPREF inputs. Nominal values are 0 mV for Y and
350 mV for PB and PR. Clamp Control Register bits
should be set as follows:
Table 4. External Clamp Setup
External clamp levels should be established to match the
incoming signals. For example, with 650 mV peak-to-peak
PBPR signals, the mid-point should be set to 325 mV.
Internal clamp timing is generated by the Timing and
Control Block. Position and width of the internal clamp
pulse, ICLAMP are programmable through registers CD and
CW. External clamp input is selected by register bit
XCLAMP and the external clamp polarity selected through
register bit XCLAMPOL. To disable the clamp for DC
coupled inputs, set XCLAMP = 1 with either of these
conditions:
1.
XCLAMPOL = 0 with input CLAMP = H.
2.
XCLAMPOL = 1 with input CLAMP = L.
Best performance will be achieved with the clamp set active
for most of the black signal level interval between the trailing
edge of horizontal sync and the start of active video. Insufcient
clamping can cause brightness changes at the top of the image
and slow recovery from large changes in Average Picture
Level (APL). Recommended clamp delay value, CD is 0x10
to 0x20 for most standard video sources.
Analog-to-Digital Converter
Figure 2 is a block diagram of the ADC core with gain and
offset functions. G7-0, OS5-0, VIN and D7-0 generically refer
to the gain and offset register values, analog input and paral-
lel data output of any RGB channel.
GYLEVEL
BPLEVEL
RPLEVEL
GBR
00
YPBPR
00
10
GYLEVEL
BPLEVEL
RPLEVEL
GBR
01
YPBPR
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