參數(shù)資料
型號(hào)： FM30C256
廠商： Electronic Theatre Controls, Inc.
英文描述： 12 AMP MINIATURE POWER RELAY
中文描述： 256Kb的數(shù)據(jù)采集器
文件頁數(shù)： 8/18頁
文件大?。?/td> 260K
代理商： FM30C256
FM30C256
Rev 2.1
Dec. 2002
Page 8 of 18
Tamper Detection and Time Stamp
The TIN pin is a battery-backed input that is used to
detect a tamper event in the system. When a rising
edge occurs on TIN, this Tamper Detect event is
recorded in the MSB of register 0. This action will
occur only when either V
BAK
or V
DD
is applied. Any
further activity on TIN, such as a falling edge, will be
ignored. The user is responsible for reading and
clearing the Tamper flag. Clearing the Tamper flag
allows the TIN to detect another rising edge. The
tamper flag can only be read or cleared when V
DD
≥
4.5V. On a power-up without battery, this bit is set to
zero.
The tamper input TIN can be used to timestamp the
exact time a tamper event occurs. This feature can be
enabled by setting the timestamp enable bit TSEN in
the calibration control register (RTC address 1, bit
D6). At power-up, TSEN is cleared and must be set
by the user. When a rising edge occurs on TIN and
the TSEN bit is set, the date and time of the event
will be recorded. The current time is loaded into the
timekeeping registers. When the system is checked
for a tamper event, the time of the event can be read.
After a tamper event, the timekeeping registers can
be overwritten if the R bit is set before reading the
timekeeping registers. To prevent overwriting the
timestamp, the control register should be read first to
check that the tamper bit is set. If it is set, the
timekeeping registers should be read to collect the
time of the last tamper event. Checking for a tamper
event before setting the R bit will ensure accurate
tamper timestamp information. If the TSEN bit is
not set, then a rising edge on TIN will not trigger a
timestamp.
System Reset Control
The /RST pin allows the user to easily control a
system level reset function. It is an open drain
output and requires an external pullup resistor to
V
DD
for proper operation. When V
DD
is within the
specified operating range, /RST output is tri-stated
and pulled to V
DD
by the external resistor. If V
DD
drops below the reset trip point voltage level (V
TP
)
and remains below this level for the V
TP
noise
immunity duration (t
RNR
), the /RST pin will be
driven low. It will continue to drive low until V
DD
falls below the V
RST
level. When V
DD
rises again
above V
TP
, /RST will continue to drive low for a
duration (t
RPU
) to ensure a robust system reset at a
reliable V
DD
level. After t
RPU
has been met, the /RST
pin tri-states and is pulled high by the external
pullup resistor. Refer to the figure on page 16 for a
graphical description of the /RST function and
timing.
9
512.0189
512.0211
512.0233
512.0256
512.0278
512.0300
512.0322
512.0344
512.0367
512.0389
512.0411
512.0433
512.0456
512.0478
512.0500
512.0522
512.0544
512.0567
512.0589
512.0611
512.0633
512.0656
512.0678
512.0211
512.0233
512.0256
512.0278
512.0300
512.0322
512.0344
512.0367
512.0389
512.0411
512.0433
512.0456
512.0478
512.0500
512.0522
512.0544
512.0567
512.0589
512.0611
512.0633
512.0656
512.0678
512.0700
36.90
41.24
45.58
49.92
54.26
58.60
62.94
67.28
71.62
75.96
80.30
84.64
88.98
93.32
97.66
102.00
106.34
110.68
115.02
119.36
123.70
128.04
132.38
41.23
45.57
49.91
54.25
58.59
62.93
67.27
71.61
75.95
80.29
84.63
88.97
93.31
97.65
101.99
106.33
110.67
115.01
119.35
123.69
128.03
132.37
136.71
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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