參數(shù)資料
型號: FM30C256
廠商: Electronic Theatre Controls, Inc.
英文描述: 12 AMP MINIATURE POWER RELAY
中文描述: 256Kb的數(shù)據(jù)采集器
文件頁數(shù): 5/18頁
文件大?。?/td> 260K
代理商: FM30C256
FM30C256
Rev 2.1
Dec. 2002
Page 5 of 18
Address
1h
/OSCEN
Description
CAL/Control
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling
the oscillator can save battery power during storage. On a power-up without battery, this bit is set to 1.
Time Stamp Enable. When set to 1, a Tamper Detect event will record the date and time of the event.
On a power-up without battery, this bit is set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base. Calibration is explained below.
These five bits control the calibration of the clock.
Flags/Control
D7
D6
D5
D4
TSEN
CALS
CAL.4
CAL.3
CAL.2
CAL.1
CAL.0
TSEN
CALS
CAL.4-0
0h
D3
D2
D1
D0
Tamper
Tamper Detect. This bit is set to 1 when rising edge is detected on the TIN pin. It can only be cleared to
0 by the user.
Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to
00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should
record the new century information as needed. This bit is cleared to 0 when the Flag register is read. It is
read-only for the user.
Invokes factory test mode. Users should always set this bit to 0.
Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock
operates normally, and the CAL pin is driven low.
Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write
them with updated values. Setting the W bit to 0 causes the contents of the time registers to be
transferred to the timekeeping counters.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a
holding register. The user can then read them without concerns over changing values causing system
errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior
to reading again.
Reserved bits. Do not use. Should remain set to 0.
CF
Reserved
Reserved
TST
CAL
W
R
Tamper
CF
TST
CAL
W
R
Reserved
Real-time Clock Operation
The real-time clock (RTC) consists of an oscillator,
divider, and a register system for accessing the
information. It divides down the 32.768 kHz time-
base and provides a minimum resolution of seconds
(1Hz) to the user. Static registers provide the user
with read/write access to the time values. The
synchronization
of
these
timekeeper core is performed using R and W bits in
register 0.
Changing the R bit from 0 to 1 causes a transfer of
the timekeeping information to holding registers that
can be read by the user. If a timekeeper update is
pending when R is set, then the update will be
completed prior to loading the registers. Another
update cannot be performed until the R bit is cleared
to 0.
Setting the W bit to 1 causes the timekeeper to freeze
updates. Clearing it to 0 causes the values in the time
registers
with
the
registers to be written into the timekeeper core. Users
should be certain not to load invalid values, such as
FFh, to the timekeeping registers.
Updates to the timekeeping core occur continuously
except when frozen. A diagram of the timekeeping
core follows.
Backup Power
The real-time clock/calendar is intended for
permanently powered operation. When the primary
system power fails, the voltage on the VDD pin will
drop. When VDD is less than the voltage on the
VBAK pin, the clock will switch to the backup power
supply. The clock operates at extremely low current
in order to maximize battery life. However, an
advantage of combining a clock function with FRAM
is that the 256K memory data is not lost regardless of
the backup power source.
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