參數(shù)資料
型號(hào): FM30C256
廠商: Electronic Theatre Controls, Inc.
英文描述: 12 AMP MINIATURE POWER RELAY
中文描述: 256Kb的數(shù)據(jù)采集器
文件頁數(shù): 10/18頁
文件大小: 260K
代理商: FM30C256
FM30C256
Rev 2.1
Dec. 2002
Page 10 of 18
Slave Address
The first byte that the FM30C256 expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the Slave ID,
Device Select address, and a bit that specifies if the
transaction is a read or a write.
The FM30C256 has two Slave Addresses (Slave
IDs) associated with two logical devices. To access
the memory device, bits 7-4 should be set to 1010b.
See Figure 4. The other logical device within the
FM30C256 is the real-time clock and tamper detect.
To access this device, bits 7-4 of the slave address
should be set to 1101b. A bus transaction with this
slave address will not affect the memory in any way.
See Figure 5.
The Slave ID bits allow other function types to
reside on the 2-wire bus for a given device select
address. The device select bits (bits 3-1) are used to
select one of eight chips on a two-wire bus. They
must match the corresponding value on the external
address pins in order to select the device. Up to eight
devices can reside on the same two-wire bus by
assigning a different address to each device. Bit 0 is
the read/write bit. A “1” indicates a read operation,
and a “0” indicates a write operation.
Slave
ID
1
0
1
0
R/W
7
6
5
4
3
2
1
0
Device
Select
A2 A1 A0
Figure 4. Slave Address - Memory
1
1
0
1
R/W
Slave
ID
7
6
5
4
3
2
1
0
Device
Select
A2
A1 A0
Figure 5. Slave Address – RTC
Addressing Overview – Memory
After the FM30C256 acknowledges the Slave
Address, the master can place the memory address
on the bus for a write operation. The address requires
two bytes. The first is the MSB (upper byte). Since
the device uses only 15 address bits, the value of the
upper bit is a “don’t care”. Following the MSB is the
LSB (lower byte) which contains the remaining eight
address bits. The address is latched internally. Each
access causes the latched address to be incremented
automatically. The current address is the value that is
held in the latch, either a newly written value or the
address following the last access. The current
address will be held as long as power remains or
until a new value is written. Accesses to the clock do
not affect the current memory address. Reads always
use the current address. A random read address can
be loaded by beginning a write operation as
explained below.
After transmission of each data byte, just prior to the
Acknowledge, the FM30C256 increments the
internal address. This allows the next sequential byte
to be accessed with no additional addressing
externally. After the last address (7FFFh) is reached,
the address latch will roll over to 0000h. There is no
limit to the number of bytes that can be accessed
with a single read or write operation.
Addressing Overview – RTC
The RTC operates in a similar manner to the
memory, except that it uses only one byte of address.
The low four bits of address specify register 0-8, and
the upper four bits are “don’t care”. Only addresses
0 through 8 should be loaded during an RTC write
command. Loading addresses 9-F is an illegal
condition and should not be attempted since
unpredictable results could occur.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM30C256 begins. For a read, the FM30C256 will
place 8 data bits on the bus then wait for an
Acknowledge from the master. If the Acknowledge
occurs, the FM30C256 will transfer the next byte. If
the Acknowledge is not sent, the FM30C256 will
end the read operation. For a write operation, the
FM30C256 will accept 8 data bits from the master
then send an Acknowledge. All data transfer occurs
MSB (most significant bit) first.
Memory Write Operation
All memory writes begin with a Slave Address, then
a memory address. The bus master indicates a write
operation by setting the slave address LSB to a 0.
After addressing, the bus master sends each byte of
data to the memory and the memory generates an
Acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 7FFFh to 0000h. Internally, the actual memory
write occurs after the 8
th
data bit is transferred. It will
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