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參數資料
| 型號： | FLEX10KE |
| 廠商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family |
| 中文描述： | 嵌入式可編程邏輯系列 |
| 文件頁數： | 7/114頁 |
| 文件大?。?/td> | 1422K |
| 代理商： | FLEX10KE |
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Altera Corporation
7
FLEX 10K Embedded Programmable Logic Family Data Sheet
Functional
Description
Each FLEX 10K device contains an embedded array to implement
memory and specialized logic functions, and a logic array to implement
general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 2,048 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input look-up
table (LUT), a programmable flipflop, and dedicated signal paths for carry
and cascade functions. The eight LEs can be used to create medium-sized
blocks of logicsuch as 8-bit counters, address decoders, or state
machinesor combined across LABs to create larger logic blocks. Each
LAB represents about 96 usable gates of logic.
Signal interconnections within FLEX 10K devices and to and from device
pins are provided by the FastTrack Interconnect, a series of fast,
continuous row and column channels that run the entire length and width
of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a flipflop that can be used as either an output
or input register to feed input, output, or bidirectional signals. When used
with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times of as low as 3.7 ns and
hold times of 0 ns; as outputs, these registers provide clock-to-output
times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
Figure 1 shows a block diagram of the FLEX 10K architecture. Each group
of LEs is combined into an LAB; LABs are arranged into rows and
columns. Each row also contains a single EAB. The LABs and EABs are
interconnected by the FastTrack Interconnect. IOEs are located at the end
of each row and column of the FastTrack Interconnect.
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| FLEX110 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Multibus Pack RoHS:否 制造商:Microchip Technology 產品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| FLEX111 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Fasttrack suite RoHS:否 制造商:Microchip Technology 產品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| FLEX112 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Demo2 Pack RoHS:否 制造商:Microchip Technology 產品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| FLEX113 | 功能描述:開發(fā)板和工具包 - 無線 Mini Kit RoHS:否 制造商:Arduino 產品:Evaluation Boards 工具用于評估:AT32UC3L 核心:AVR32 頻率: 接口類型:USB 工作電源電壓:5 V |
| FLEX114 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Demo2 suite RoHS:否 制造商:Microchip Technology 產品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
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