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參數(shù)資料
| 型號： | FLEX10KE |
| 廠商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family |
| 中文描述： | 嵌入式可編程邏輯系列 |
| 文件頁數(shù)： | 17/114頁 |
| 文件大?。?/td> | 1422K |
| 代理商： | FLEX10KE |
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Altera Corporation
17
FLEX 10K Embedded Programmable Logic Family Data Sheet
Cascade Chain
With the cascade chain, the FLEX 10K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical
or logical
OR
(via De Morgans inversion) to connect the outputs of
adjacent LEs. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.7 ns per LE. Cascade
chain logic can be created automatically by the MAX+PLUS II Compiler
during design processing, or manually by the designer during design
entry.
AND
Cascade chains longer than eight bits are automatically implemented by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB.) The cascade chain
does not cross the center of the row (e.g., in the EPF10K50 device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
nineteenth LAB). This break is due to the EABs placement in the middle
of the row.
Figure 8 shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. These examples show functions of 4
n
variables implemented with
n
LEs. The LE delay is as low as 1.9 ns; the
cascade chain delay is as low as 0.7 ns. With the cascade chain,
approximately 4.2 ns is needed to decode a 16-bit address.
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