參數(shù)資料
型號： FC106
廠商： Sanyo Electric Co.,Ltd.
英文描述： NPN Epitaxial Planar Silicon Composite Transistor Switching Applications
中文描述： 瑞展復(fù)合硅晶體管的開關(guān)應(yīng)用
文件頁數(shù)： 25/32頁
文件大?。?/td> 210K
代理商： FC106
FC106
Revision 1.2
25/32
September 98
7
FC106 Pin Description
7.1
Pin summary
Table 7.1
Pin summary
Pin
Level
Description
AT*
CMOS
This signal places the chip in a self-test mode when tied low. It should be
tied to V
dd
in any other state of the chip, as specified in the 10-Bit Interface
Specification standard.
COM_DET is an indication that the data byte (byte 0 of word 0) associated
with the current RBC[1] contains a valid comma symbol.
EN_CDET enables the chip to perform the byte alignment function on
comma symbols. When EN_CDET is high, the byte alignment function is
operational.
When EN_CDET is low, the current byte alignment is maintained.
EWRAP causes the chip to internally loop serialized transmit data to the
deserializer. EWRAP is active on high level.
RBC[0] is the 53.125 MHz receive byte clock that the protocol device will
use to register the bytes 1 and 3 of the received data word. This clock may
be stretched during byte alignment (neverslivered or truncated).
RBC[1] is the 53.125 MHz receive byte clock that the protocol device will
use to register the bytes 0 and 2 of the received data word. RBC[1] is 180
°
out of phase with RBC[0]. This clock may be stretched during byte align-
ment (never slivered or truncated).
REFCLK is the 106.25 MHz reference clock. The frequency tolerance for
this clock should meet ANSI X3.230-1994 Fibre Channel FC-PH specifica-
tions for a Fibre Channel use. See Section 6.1:Transmit interface timing
and latencyon page 20.
RX+ and RX- are the differential inputs for serialized data on the receiver.
RX[0:9] is the 10-bit parallel received data presented by the chip to the
upper layer for further processing. The received data byte 0 containing the
comma symbol will be byte aligned to RBC[1], i.e. byte 0 is in phase with
RBC[1]. The order of reception on the serial input is RX[0] first, followed by
RX[1] through to RX[9].
These signals are compliant to the JTAG specification.
COM_DET
CMOS
EN_CDET
CMOS
EWRAP
CMOS
RBC[0]
CMOS
RBC[1]
CMOS
REFCLK
CMOS
RX+, RX-
RX[0:9]
Special
CMOS
TCK*,
TRSTN*,
TMS*, TDI*,
TDO*
TEST
ENABLE*
TX+, TX-
CMOS
CMOS
Used during ATPG test, connected at V
ss
in normal operation.
Special
TX+ and TX- are the differential outputs for serialized data on the
transmitter.
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