參數(shù)資料
型號： FC106
廠商： Sanyo Electric Co.,Ltd.
英文描述： NPN Epitaxial Planar Silicon Composite Transistor Switching Applications
中文描述： 瑞展復(fù)合硅晶體管的開關(guān)應(yīng)用
文件頁數(shù)： 20/32頁
文件大?。?/td> 210K
代理商： FC106
FC106
Revision 1.2
20/32
September 98
6
Timing Specifications
All AC measurements are made from the reference voltage level of the clock (1.4 volts), to
the valid input or output data levels.
6.1
Transmit interface timing and latency
Figure 6.1
Transmit interface timing and latency
Table 6.1
Transmit interface timing characteristics
Parameter
Description
Min
Typ
Max
Units
F
ref
=1/T
ref
Ftol
Reference clock frequency
Frequency tolerance (dispersion between
REFCLK of transmitter and receiver chips)
REFCLK Clock Rise Time (0.8 to 2V)
100
100
106.25 110
-
MHz
ppm
+ 100
Tr
Tf
CLKJIT
DT
Tsu_tx
Th_tx
TX-Tr,Tf
T
ELA
0.6
-
2.4
nS
REFCLK Clock Fall Time (0.8 to 2V)
0.6
-
2.4
nS
REFCLK Jitter
REFCLK duty Cycle
Data set-up to a rising edge of REFCLK
Data hold after a rising edge of REFCLK
Parallel data rise and fall time (10 pF load)
Data Emission Latency (delay from the initial
10-bit word load to the serial transmission of bit 0)
40
60
-
-
3
1 REFCLK
cycle + 8 ns
pS
%
ns
ns
ns
40
0
1.5
0.6
-
-
-
-
-
-
VALID
DATA 3
TX[0:9]
REFCLK
Tsu_tx
Th_tx
T
ref
VALID
DATA 1
VALID
DATA 2
1.4V
1.4V
2.0V
0.8V
TX+
bit 0 of parallel in-
put (TX0ofDATA1)
T
ELA
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