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參數(shù)資料
| 型號： | FC106 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | NPN Epitaxial Planar Silicon Composite Transistor Switching Applications |
| 中文描述： | 瑞展復(fù)合硅晶體管的開關(guān)應(yīng)用 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 210K |
| 代理商： | FC106 |
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FC106
Revision 1.2
11/32
September 98
example, if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate
must be 1.0625
±
0.0001 Gb/s.
The FC106 provides 2 TTL recovered clocks RBC[0] and RBC[1], which are both driven at a
frequency of one twentieth of the serial signaling rate. These clocks are generated by the
clock recovery DLL, which is phase locked to the serial data. RBC[1] is 180
°
out of phase
with RBC[0]. If serial data is not present, or does not meet the required transition density or
signaling rate, the RBC frequencies will be half of the expected recovered clock frequency
(defined by REFCLK). This function replaces the optional LCK_REF signal that is specified
in the Fibre Channel 10-bit interface. When no data is present, phase adjustments are
required for switching between a locking to incoming data and locking to REFCLK. The
specification on output clocks RBC[0:1] is maintained during these adjustments.The clock
periods are not truncated.
The serial data is retimed and deserialized. Parallel data is loaded into the output register,
and therefore accessible on the output data port. For Fibre Channel use, bytes 1 and 3 of the
receive data word will be accessible on the rising edge of RBC[0], and bytes 0 and 2 on the
rising edge of RBC[1].
Word synchronization is enabled in the FC106 by connecting the EN_CDET pin to V
dd
.
When EN_CDET is set high, the FC106 examines serial data for the presence of a positive
disparity comma symbol (0011111). Improper alignment occurs when a comma symbol
straddles a 10-bit boundary or is not aligned within the 10-bit transmission character. Proper
alignment is reached by shifting the boundary of the parallel output.
At power up the FC106 will not be in synchronization and data alignment is not established.
The COM_DET output signal is then set low.When a comma symbol is detected, COM_DET
is set high (if EN_CDET is already set high). COM_DET will go high only during a cycle in
which RBC[1] is rising (see Section 6.2.2: Receive interface timing on page 23 for precise
timing).
Note that if EN_CDET is set low, but a comma is detected while the input stream is already
word-aligned, COM_DET will be set high again.
3.9
Bit alignment
The alignment block aligns the incoming data bit stream and the reference clocks generated
by the DLL Clock Generator. It compensates for clock frequency dispersions between the
crystals generating the respective reference clocks REFCLK of the transmitting and
receiving chips.
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相關(guān)代理商/技術(shù)參數(shù) |
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| FC10600-0 | 制造商:Amphenol Corporation 功能描述:LEAD 2.54MM F/F 600MM 10WA 制造商:Amphenol Aerospace 功能描述:LEAD, 2.54MM, F/F, 600MM, 10WAY 制造商:Amphenol Corporation 功能描述:LEAD, 2.54MM, F/F, 600MM, 10WAY; Connector Type A:IDC Female; Connector Type B:IDC Socket; No. of Conductors:10; Pitch Spacing:2.54mm; Cable Length - Imperial:23.622"; Cable Length - Metric:600mm; Jacket Colour:Grey; SVHC:No SVHC ;RoHS Compliant: Yes |
| FC10600-S | 制造商:Amphenol Corporation 功能描述:LEAD 2.54MM F/F S/R 600MM 制造商:Amphenol Aerospace 功能描述:LEAD, 2.54MM, F/F, S/R, 600MM, 10WAY 制造商:Amphenol Corporation 功能描述:LEAD, 2.54MM, F/F, S/R, 600MM, 10WAY; Connector Type A:IDC Female; Connector Type B:IDC Socket; No. of Conductors:10; Pitch Spacing:2.54mm; Cable Length - Imperial:23.622"; Cable Length - Metric:600mm; Jacket Colour:Grey; SVHC:No ;RoHS Compliant: Yes |
| FC1-06-01-T | 制造商:Samtec Inc 功能描述:CONN FFC/FPC CONN SKT 6 POS 1MM SLDR ST SMD - Bulk |
| FC1-06-01-T-K | 制造商:Samtec Inc 功能描述:CONN FFC/FPC CONN SKT 6 POS 1MM SLDR ST SMD - Bulk |
| FC1-06-01-T-K-TR | 制造商:Samtec Inc 功能描述:CONN FFC/FPC CONN SKT 6 POS 1MM SLDR ST SMD - Tape and Reel |
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