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參數資料
| 型號： | FC106 |
| 廠商： | 意法半導體 |
| 英文描述： | Fibre Channel Transceiver 1.0625 GBaud |
| 中文描述： | 光纖通道收發(fā)器1.0625 GBaud |
| 文件頁數： | 9/32頁 |
| 文件大?。?/td> | 210K |
| 代理商： | FC106 |
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FC106
Revision 1.2
9/32
September 98
3.3
8bit/10bit Encoder/Decoder
In normal operation mode, the FC106 accepts 10-bit pre-encoded data, and provides to the
application, 10-bit encoded data (as specified in the ANSI 10-bit Interface Specification).
In addition, the FC106 contains an 8b/10b encoder/decoder, which can be inserted into the
data flow. The selection of this mode is made through the JTAG path. In this mode, the
FC106 accepts and delivers bytes on 9 bits (8 bits of data on TX/RX[0:7] and 1 bit on TX/
RX[8] which is used to differentiate control characters). The timings of the parallel I/O ports
are identical in both modes: using the 8b/10b encoder/decoder increases the transmission
latency by 2 byte clock periods (equivalent to a 4 meter increase of the cable length).
3.4
DLL clock generator
The DelayLocked Loop (DLL) block generates the internal clocks. These are required by the
transmitter section to perform its function, and by the receiver block to generate the
reference clocks which are used to recover the serial data input frequency. These clocks are
based on the user supplied reference byte clock REFCLK. This clock is multiplied by 10 to
generate the required serial output data rate. No external components are required to
operate the DLL Clock Generator.
3.5
Serializer functional description and reference
clock
The FC106 serializer performs the serialization of 10-bit pre-encoded parallel data at
signaling rates up to 1.0625 Gb/s. System design is simplified by the integration into the chip
of a block performing clock multiplication from the parallel data clock.
It accepts 10-bit encoded parallel data words which are clocked into the device at 1/10 of the
signaling rate. For Fibre Channel use, data should be encoded for transmission using the
8B/10B block code described in the Fibre Channel specification. The FC106 serializes the
input data and transmits it at a signaling rate of 10 times the frequency of the REFCLK input.
The device includes a Delay-Locked-Loop based clock multiplier that generates the
1.0625 Gbaud clocks. This DLL is fully monolithic and requires no external components. Its
acquisition time, at power-up, is less than 16 microseconds.
The FC106 loads parallel data on the rising edge of REFCLK. The delay through the FC106
from loading the code-group to the transmission of the first bit of the code-group on the TX+,
TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding function is enabled.
A loop-back-mode signal EWRAP is provided allowing internal dynamic self-test of the chip.
When EWRAP is low, the output of the transmitter is sent to the TX+ and TX- output pins,
and the input of the receiver is driven by the signals entered through the RX+ and RX- pins.
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| FC10600-0 | 制造商:Amphenol Corporation 功能描述:LEAD 2.54MM F/F 600MM 10WA 制造商:Amphenol Aerospace 功能描述:LEAD, 2.54MM, F/F, 600MM, 10WAY 制造商:Amphenol Corporation 功能描述:LEAD, 2.54MM, F/F, 600MM, 10WAY; Connector Type A:IDC Female; Connector Type B:IDC Socket; No. of Conductors:10; Pitch Spacing:2.54mm; Cable Length - Imperial:23.622"; Cable Length - Metric:600mm; Jacket Colour:Grey; SVHC:No SVHC ;RoHS Compliant: Yes |
| FC10600-S | 制造商:Amphenol Corporation 功能描述:LEAD 2.54MM F/F S/R 600MM 制造商:Amphenol Aerospace 功能描述:LEAD, 2.54MM, F/F, S/R, 600MM, 10WAY 制造商:Amphenol Corporation 功能描述:LEAD, 2.54MM, F/F, S/R, 600MM, 10WAY; Connector Type A:IDC Female; Connector Type B:IDC Socket; No. of Conductors:10; Pitch Spacing:2.54mm; Cable Length - Imperial:23.622"; Cable Length - Metric:600mm; Jacket Colour:Grey; SVHC:No ;RoHS Compliant: Yes |
| FC1-06-01-T | 制造商:Samtec Inc 功能描述:CONN FFC/FPC CONN SKT 6 POS 1MM SLDR ST SMD - Bulk |
| FC1-06-01-T-K | 制造商:Samtec Inc 功能描述:CONN FFC/FPC CONN SKT 6 POS 1MM SLDR ST SMD - Bulk |
| FC1-06-01-T-K-TR | 制造商:Samtec Inc 功能描述:CONN FFC/FPC CONN SKT 6 POS 1MM SLDR ST SMD - Tape and Reel |
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