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參數(shù)資料
| 型號(hào)： | FC106 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Fibre Channel Transceiver 1.0625 GBaud |
| 中文描述： | 光纖通道收發(fā)器1.0625 GBaud |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 210K |
| 代理商： | FC106 |
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FC106
Revision 1.2
26/32
September 98
7.2
Pin functions
Table 7.2
Pin functions
TX[0:9]
CMOS
TX[0:9] is the 10-bit parallel transmit data presented to the chip for serial-
ization and transmission onto the media. The order of transmission is TX[0]
through to TX[9].
These pins are used to control the input and output impedance in accor-
dance with the configuration outlined in Section 3.13:I/O impedance con-
trolon page 14.
ZC+
1
, ZC-*
CMOS
1.
indicates signals that are not included in the Fibre Channel 10-Bit Interface Specification.
Pin Name
Pin #
I/O
pull up/
down
Description in standard running conditions
TEST
pins
V
ss
TX[0]
TX[1]
TX[2]
V
dd
TX[3]
TX[4]
TX[5]
TX[6]
V
dd
TX[7]
TX[8]
TX[9]
V
ss
V
ss
/RS
1
2
3
4
5
6
7
8
9
10
-
I
I
I
-
I
I
I
I
-
-
pd
pd
pd
-
pd
pd
pd
pd
-
Ground Pin
Bit 0 of parallel transmit data (first bit sent)
Bit 1 of parallel transmit data
Bit 2 of parallel transmit data
Power Pin
Bit 3 of parallel transmit data
Bit 4 of parallel transmit data
Bit 5 of parallel transmit data
Bit 6 of parallel transmit data
Power Pin
11
12
13
14
I
I
I
-
pd
pd
pd
-
Bit 7 of parallel transmit data
Bit 8 of parallel transmit data
Bit 9 of parallel transmit data (last bit sent)
Ground Pin
15
(I)
pd
Must be tied to GND during normal operation.
During power up, an internal circuit will
automatically reset the chip. Nevertheless RS
allows a forced reset (when high), during normal
operation.
Not connected
External
reset
NC/TDI
16
(I)
pd
JTAG
scan in
Test clock
pin for
JTAG
NC/TCK
17
(I)
pd
Not connected
Pin
Level
Description
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