參數(shù)資料
型號(hào)： FC106
廠商： 意法半導(dǎo)體
英文描述： Fibre Channel Transceiver 1.0625 GBaud
中文描述： 光纖通道收發(fā)器1.0625 GBaud
文件頁(yè)數(shù)： 27/32頁(yè)
文件大?。?/td> 210K
代理商： FC106
FC106
Revision 1.2
27/32
September 98
V
dd
/TRSTN
18
(I)
pu
Must be tied to V
dd
.
Reset pin
for JTAG
EWRAP
19
I
pd
When tied to V
dd
, causes the chip to internally
loop serialized transmit data to the deserializer.
Must be tied to V
dd
.
V
dd
/TMS
20
(I)
pu
Test mode
select for
JTAG
V
ss
REFCLK
V
dd
EN_CDET
21
-
-
Ground Pin
22
23
24
I
I
I
pd
-
pu
Reference clock frequency 106.25 MHz
Power Pin
Enables the chip to perform the byte alignment
function when HIGH.
Must be tied to GND.
TEST
ENABLE
NC/TDO
25
I
pd
Tie to V
dd
for AT PG
JTAGscan
out
26
(O)
-
Not connected
NC
V
dd
/AT
27
28
-
(I)
-
pu
Not connected
Must be tied to V
dd
.
Places the
chip in
auto test
mode
when
LOW.
V
dd
RBC[1]
29
30
-
O
Power Pin
Receive byte clock used by the protocol to
register byte 0 and 2 of the receive parallel data.
Receive byte clock used by the protocol to
register byte 1 and 3 of the receive parallel data.
Ground Pin
-
RBC[0]
31
O
-
V
ss
V
ss
RX[9]
RX[8]
RX[7]
V
dd
RX[6]
RX[5]
RX[4]
RX[3]
V
dd
32
-
-
33
-
-
Ground Pin
34
35
36
37
38
39
40
41
42
O
O
O
-
O
O
O
O
-
-
-
-
-
-
-
-
-
-
Bit 9 of parallel receive data (last bit received)
Bit 8 of parallel receive data
Bit 7 of parallel receive data
Power Pin
Bit 6 of parallel receive data
Bit 5 of parallel receive data
Bit 4 of parallel receive data
Bit 3 of parallel receive data
Power Pin
Pin Name
Pin #
I/O
pull up/
down
Description in standard running conditions
TEST
pins
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