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參數(shù)資料
| 型號(hào)： | FBL2033BB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V BTL 8-bit latched/registered/pass-thru universal transceiver |
| 中文描述： | FBL SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 150K |
| 代理商： | FBL2033BB |
Philips Semiconductors
Product specification
FBL2033
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
1999 Apr 15
3
DESCRIPTION
The FBL2033 is an 8-bit transceiver featuring a split input (AI) and
output (AO) bus on the TTL-level side.
The common I/O, open collector B port operates at BTL signal
levels. The logic element for data flow in each direction is controlled
by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A,
SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a
register, or a D-type latch.
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-High latch enables.
Regardless of the mode, data is inverted from input to output.
Data flow in the B-to-A direction, regardless of the logic element
selected, is further controlled by the Loopback input. When the
Loopback input is High the output of the selected A-to-B logic
element (not inverted) becomes the B-to-A input.
The 3-State AO port is enabled by asserting a High level on OEA.
The B port has two output enables, OEB0 and OEB1. Only when
OEB0 is High and OEB1 is Low is the output enabled. When either
OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to
the level of the pull-up voltage. New data can be entered in the
flip-flop and latched modes or can be retained while the associated
outputs are in 3-State (AO port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port ensure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to “Backplane Transceiver Logic” (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The “V
OH
” clamp reduces inductive ringing effects
during a Low-to-High transition. The “V
OH
” clamp is always active.
The other clamp, the “trapped reflection” clamp, clamps out ringing
below the BTL 0.5V V
OL
level. This clamp remains active for
approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off
cycles to ensure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
CC
is Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble- shoot.
As with any high power device thermal considerations are
critical. It is recommended that airflow (300Ifpm) and/or thermal
mounting be used to ensure proper junction temperature.
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
AI0 – AI7
50, 52, 3, 5, 8, 10, 12, 15
Input
Data inputs (TTL)
AO0 – AO7
51, 2, 4, 6, 9, 11, 14, 16
Output
3-State outputs (TTL)
40, 38, 36, 34, 32, 30, 28, 26
I/O
Data inputs/Open Collector outputs, High current drive (BTL)
OEB0
23
Input
Enables the B outputs when High
OEB1
24
Input
Enables the B outputs when Low
OEA
43
Input
Enables the AO outputs when High
BUS GND
39, 37, 35, 33, 31, 29, 27, 25
GND
Bus ground (0V)
LOGIC GND
1, 13, 17, 49
GND
Logic ground (0V)
V
CC
18, 22, 48
Power
Positive supply voltage
BIAS V
41
Power
Live insertion pre-bias pin
BG V
CC
44
Power
Band Gap threshold voltage reference
BG GND
42
GND
Band Gap threshold voltage reference ground
SABn
20, 21
Input
Mode select from AI to B
SBAn
45, 46
Input
Mode select from B to AO
LCAB
47
Input
A-to-B clock/latch enable (transparent latch when High)
LCBA
19
Input
B-to-A clock/latch enable (transparent latch when High)
Loopback
7
Input
Enables loopback function when High (from AIn to AOn)
相關(guān)PDF資料 |
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|---|---|
| FBL2040 | 3.3V BTL8-bit TTL to BTL transceiver |
| FBL2040BB | 3.3V BTL8-bit TTL to BTL transceiver |
| FBL2041 | 3.3V BTL 7-bit Futurebus transceiver standard A-port |
| FBL2041BB | 3.3V BTL 7-bit Futurebus transceiver standard A-port |
| FBL2041I | 3.3V BTL 7-bit Futurebus transceiver standard A-port |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FBL2040 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL8-bit TTL to BTL transceiver |
| FBL2040BB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL8-bit TTL to BTL transceiver |
| FBL2041 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL 7-bit Futurebus transceiver standard A-port |
| FBL2041BB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V BTL 7-bit Futurebus transceiver standard A-port |
| FBL2041BB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:7-Bit Bus Transceiver |
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