參數(shù)資料
型號: FBL2033BB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
中文描述: FBL SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52
文件頁數(shù): 10/14頁
文件大?。?/td> 150K
代理商: FBL2033BB
Philips Semiconductors
Product specification
FBL2033
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
1999 Apr 15
10
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C, V
CC
= 3.3V
T
amb
= –40 to +85
°
C,
V
CC
= 3.3V
±
10%
UNIT
C
L
= 50pF (A side) / C
D
= 30pF (B side)
R
L
= 500
(A side) / R
U
= 9
(B side)
MIN
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
h
(H)
t
h
(L)
t
h
(H)
t
h
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
Hold time (latch mode)
AIn to LCAB
6.0
5.0
6.5
5.5
ns
Hold time (register mode)
AIn to LCAB
1.0
1.0
1.3
1.3
ns
Hold time (latch mode)
Bn to LCAB
1.5
1.5
2.0
2.0
ns
Hold time (register mode)
Bn to LCAB
1.0
1.0
1.3
1.3
ns
Pulse width, High or Low
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C, V
CC
= 3.3V
T
amb
= –40 to +85
°
C,
CC
= 3.3V
±
10%
UNIT
C
L
= 50pF (A side) / C
D
= 30pF (B side)
R
L
= 500
(A side) / R
U
= 16.5
(B side)
MIN
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
h
(H)
t
h
(L)
t
h
(H)
t
h
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
Hold time (latch mode)
AIn to LCAB
6.0
5.0
6.5
5.5
ns
Hold time (register mode)
AIn to LCAB
1.0
1.0
1.3
1.3
ns
Hold time (latch mode)
Bn to LCAB
1.5
1.5
2.0
2.0
ns
Hold time (register mode)
Bn to LCAB
1.0
1.0
1.3
1.3
ns
Pulse width, High or Low
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
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