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參數(shù)資料
| 型號： | FAN9612MX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 1561K |
| 描述： | IC CTLR PFC DUAL BCM 16SOICN |
| 標準包裝： | 1 |
| 模式： | 臨界傳導(dǎo)（BCM） |
| 頻率 - 開關(guān)： | 16.5kHz ~ 525kHz |
| 電流 - 啟動： | 80µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 標準包裝 |
| 其它名稱： | FAN9612MXFSDKR |
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?2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN9612 " Rev. 1.1.7
14
Figure 20. Error Amplifier Compensation Circuitry
7. Output Voltage Feedback (FB)
The feedback pin receives the divided-down output
voltage of the converter. In regulation, the FB pin should
be 3 V, which is the reference used at the non-inverting
input of the error amplifier. Due to the g
M
type error
amplifier, the FB pin is always proportional to the output
voltage and can be used for over-voltage protection as
well. A non-latching over-voltage detection circuit
monitors the FB pin and prevents the boost MOSFETs
from turning on when the FB voltage exceeds 3.25 V.
Operation resumes automatically when the FB voltage
returns to its nominal 3 V level.
The open feedback detection circuit is also connected to
the FB pin. Since the output of the boost converter is
charged to the peak of the input AC voltage when power
is applied to the power supply, the detection circuit
monitors the presence of this voltage. If the FB pin is
below 0.5 V, which would indicate a missing feedback
divider (or wrong value causing dangerously-high
regulation voltage), the FAN9612 does not send out
gate drive signals to the boost transistors.
Figure 21. Output-Voltage Feedback Circuit
8. Secondary Output Voltage Sense (OVP)
A second-level latching over-voltage protection can be
implemented using the OVP pin of the controller. The
threshold of this circuit is set to 3.5 V. There are two
ways to program the secondary OVP.
Option 1, as shown in Figure 22, is to connect the OVP
pin to the FB pin. In addition to the standard non-
latching OVP (set at ~8%), this configuration provides a
second OVP protection (set at ~15%), which is latched.
In the case where redundant over-voltage protection is
preferred (also called double-OVP protection), a second
separate divider from the output voltage can be used, as
shown by Option 2 in Figure 22. In this case, the
latching OVP protection level can be independently
established below or above the non-latching OVP
threshold, which is based on the feedback voltage (at
the FB pin).
If latching OVP protection is not desired at all, the OVP
pin should be grounded (Option 3).
Figure 22. Secondary Over-Voltage Protection
Circuit
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