參數(shù)資料
型號： FAN9611MX
廠商： Fairchild Semiconductor
文件頁數(shù)： 19/35頁
文件大?。?/td> 1556K
描述： IC PFC CTLR DUAL BCM 16-SOIC
標(biāo)準(zhǔn)包裝： 1
系列： Sync-Lock™
模式： 臨界傳導(dǎo)（BCM）
頻率 - 開關(guān)： 16.5kHz ~ 525kHz
電流 - 啟動： 80µA
電源電壓： 9 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： FAN9611MXFSDKR
 
?2008 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN9611 " Rev. 1.1.7
19
 
Figure 28. Adjusting Phase Management Thresholds
Since the phase management threshold is fixed at 13%
and 18% of the maximum power limit level, the actual
power   management   threshold   as   a   percentage   of
nominal output power can be adjusted by the ratio
between nominal power and maximum power limit level
as shown in Figure 28. The second plot shows an
example where the maximum power limit level is 1.4
times   of   nominal   output   power.   By   adjusting   the
maximum on-time (using R
MOT
), the phase management
thresholds can be adjusted upward.
Phase   management   is   implemented   such   that   the
output of the error amplifier (V
COMP
) does not have to
change when the system toggles between single-phase
and two-phase operations, as shown in Figure 29. The
output of the error amplifier is proportional to the output
power of the converter independently, whether one or
both   phases   are   operating   in   the   power   supply. 
Furthermore, because the maximum on-time limit is
applied independently to each pulse-width modulator,
the power handling capability of the converter with only
one phase running is approximately half of the total
output power that can be delivered when both phases
are utilized.
Additional details on adjusting phase management are
provided in the application note AN-6086.
 
Figure 29. V
COMP
 vs. t
ON
MAX
 
5.   Disabling the FAN9611
There are four ways to disable the FAN9611. It is
important to understand how the part reacts for the
various shutdown procedures.
a.    Pull the SS Pin to GND
. This method uses the error
amplifier to stop the operation of the power supply.
By pulling the SS pin to GND, the error amplifiers
non-inverting input is pulled to GND. The amplifier
senses that the inverting input (FB pin) is higher
than the reference voltage and tries to adjust its
output (COMP pin) to make the FB pin equal to the
reference at the SS pin. Due to the slow speed of
the voltage loop in PFC applications, this might take
several line cycles. Thus, it is important to consider
that by pulling the SS pin to GND, the power supply
is not shut down immediately. Recovery from a shut
down follows normal soft-start procedure when the
SS pin is released.
b.    Pull the FB Pin to GND
. By pulling the FB pin below
the    open    feedback    protection    threshold    of
approximately 0.5 V, the power supply can be shut
down immediately. It is imperative that the FB is
pulled below the threshold very quickly since the
power supply keeps switching until this threshold is
crossed. If the feedback is pulled LOW softly and
does not cross the threshold, the power supply tries
to deliver maximum power because the FB pin is
forced below the reference voltage of the error
amplifier on the SS pin. Eventually, as FB is pulled
to GND, the SS capacitor is pulled LOW by the
internal clamp between the FB and SS pins. The
SS pin stays approximately 0.5 V higher than the
FB pin itself. Therefore, recovery from a shut down
state follows normal soft-start procedure when the
FB pin is released as the voltage across the SS
capacitor starts ramping from a low value.
c.    Pulling the COMP Pin to GND
. When the COMP
pin   is   pulled   below   the   PWM   ramp   offset,
approximately 0.195 V, the FAN9611 stops sending
gate drive pulses to the power MOSFETs. This
condition is similar to pulse skipping under no-load
condition. If any load is still present at the output of
the boost PFC stage, the output voltage decreases.
Consequently, the FB pin decreases and the SS
capacitor voltage is pulled LOW by the internal
clamp between the FB and SS pins. At that point,
the operation and eventual recovery to normal
operation is similar to the mechanism described
above. If the COMP pin is held LOW for long
enough to pull the SS pin LOW, the recovery
follows normal soft-start procedure when the COMP
pin is released. If the SS capacitor is not pulled
LOW as a result of a momentary pull-down of the
COMP pin, the recovery is still soft due to the fact
that   a   limited   current   source   is   charging   the
compensation capacitors at the output of the error
amplifier. Nevertheless, in this case, output voltage
overshoot can occur before the voltage loop enters
closed-loop operation and resumes controlling the
output voltage again.
d.    Pull the VIN Pin to GND
. Since the VIN sense
circuit is configured to ride through a single line
cycle dropout test without shutting down the power
supply, this method results in a delayed shutdown
of the converter. The FAN9611 stops operation
approximately 20 ms to 32 ms after the VIN pin is
pulled LOW. The delay depends on the phase of
the line cycle at which the pull-down occurs. This
method triggers the input brownout protection (input
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