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參數(shù)資料
| 型號： | FAN9611MX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 18/35頁 |
| 文件大小： | 1556K |
| 描述： | IC PFC CTLR DUAL BCM 16-SOIC |
| 標準包裝： | 1 |
| 系列： | Sync-Lock™ |
| 模式： | 臨界傳導（BCM） |
| 頻率 - 開關： | 16.5kHz ~ 525kHz |
| 電流 - 啟動： | 80µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | FAN9611MXFSDKR |
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?2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN9611 " Rev. 1.1.7
18
Application Information
1. Synchronization and Timing Functions
The FAN9611 employs a sophisticated synchronization
sub-system. At the heart of the system is a dual-channel
switching-frequency detector that measures the
switching period of each channel in every switching
cycle and locks their operating phase 180 degrees out
of phase from each other. The slower operating
frequency channel is dominant, but there is no master-
slave arrangement. Moreover, as the frequency
constantly changes due to the varying input voltage,
either channel can be the slower dominant channel.
As opposed to the most common technique, where the
phase relationship between the channels is provided by
changing the on-time of one of the MOSFETs, the
FAN9611 controls the phase relationship by inserting a
turn-on delay before the next switching period starts for
the faster running phase. As shown in the literature
[1]
,
the on-time modulation technique is not stable under all
operating conditions, while the off-time modulation (or
delaying the turn-on) is unconditionally stable under all
operating conditions.
a. Restart Timer and Dead-Phase Detect
Protection
The restart timer is an integral part of the Sync-Lock"
synchronizing circuit. It ensures exact 180-degree out-
of-phase operation in restart timer operation. This is an
important safety feature. In the case of a non-operating
phase due to no ZCD detection, missing gate drive
connection (for example no gate resistor), one of the
power components failing in an open circuit, or similar
errors, the other phase is locked into restart timer
operation, preventing it from trying to deliver full power
to the load. This is called the dead-phase detect
protection.
The restart timer is set to approximately 16.5 kHz, just
above the audible frequency range, to avoid any
acoustic noise generation.
b. Frequency Clamp
Just as the restart timer, the frequency clamp is
integrated into the synchronization and ensures exact
180-degree out-of-phase operation when the operating
frequency is limited. This might occur at very light-load
operation or near the zero crossing region of the line
voltage waveform. Limiting the switching frequency at
light load can improve efficiency, but has a negative
effect on power factor since the converter also enters
true DCM operation. The frequency clamp is set to
approximately 525 kHz.
2. Adjusting the Output Voltage with Load
Some applications, the output voltage of the PFC boost
converter is decreased at low power levels to boost the
light load efficiency of the power supply.
Implementing this function with a circuit external to the
FAN9611 is straightforward because the error amplifier
reference (the positive input) is available on the soft-
start (SS) pin, as shown in Figure 27. In the FAN9611
architecture, the power of the converter is proportional
to the voltage on the COMP pin, minus a small offset.
The voltage on the COMP pin is monitored to determine
the operating power of the supply. Therefore the voltage
on the SS pin can be adjusted lower to achieve the
desired lower output voltage.
Several possible implementations to adjust the output
voltage of the boost stage at light load are described in
the application note AN-8021. It includes the universal
output voltage adjust implementation which is
modulated by input voltage to avoid the boost converter
becoming a peak rectifier at high line and light load.
Figure 27. FAN9611 Error Amplifier Configuration
3. Adjusting the Output Voltage with Input
Voltage
In some applications, the output voltage of the PFC
boost converter is adjusted based on the input voltage
only. This boost follower implementations increases the
efficiency of the downstream DC-DC converter and
therefore of the overall power supply.
Implementations for both the two-level boost and the
linear boost follower (or tracking boost) are described in
application note AN-8021.
4. Adjusting the Phase-Management
Thresholds
In any power converter, the switching losses become
dominant at light load. For an interleaved converter
where there are two or more phases, light-load
efficiency can be improved by shutting down one of the
phases at light load (also known as phase-shedding or
phase-dropping operating).
The initial phase-management thresholds are fixed at
approximately 13% and 18% of the maximum load
power level. This means when the output power
reaches 13%, the FAN9611 automatically goes from a
two-phase to a single-phase operation (phase shed or
phase drop). When the output power comes back up to
18%, the FAN9611 automatically goes from the single-
phase to the two-phase operation (phase-add).
The default thresholds can be adjusted upward based
on the application requirement; for example, to meet the
Energy STAR 5.0 or the Climate Savers Computing
efficiency requirements at 20% of the load. The phase
drop threshold can be adjusted upward (for example to
25%) by adjusting the maximum on time.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FAN9612 | 制造商:Fairchild 功能描述:INTERLEAVED PFC IC |
| FAN9612M | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| FAN9612MX | 功能描述:功率因數(shù)校正 IC Interleaved Dual BCM PFC Controller RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| FAN9612Y FAN9613Y WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| FAN9613_YAC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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