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參數(shù)資料
| 型號： | FAN9611MX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 13/35頁 |
| 文件大小： | 1556K |
| 描述： | IC PFC CTLR DUAL BCM 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Sync-Lock™ |
| 模式： | 臨界傳導(dǎo)（BCM） |
| 頻率 - 開關(guān)： | 16.5kHz ~ 525kHz |
| 電流 - 啟動： | 80µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FAN9611MXFSDKR |
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?2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN9611 " Rev. 1.1.7
13
4. Analog Ground (AGND) and Power Ground
(PGND)
Analog ground connection (AGND) is the GND for all
control logic biased from the 5 V rail. Internally, the
AGND and PGND pins are tied together by two anti-
parallel diodes to limit ground bounce difference due to
bond wire inductances during the switching actions of
the high-current gate drive circuits. It is recommended to
connect AGND and PGND pins together with a short,
low-impedance trace on the PCB (right under the IC).
PGND is the reference potential (0 V) for the high-
current gate-drive circuit. Two bypass capacitors should
be connected between the VDD pin and the PGND pin.
One is the V
DD
energy storage capacitor, which provides
bias power during startup until the bootstrap power
supply comes up. The other capacitor shall be a good-
quality ceramic bypass capacitor, as close as possible
to PGND and VDD pins to filter the high peak currents
of the gate driver circuits. The value of the ceramic
bypass capacitor is a strong function of the gate charge
requirement of the power MOSFETs and its
recommended value is between 1 礔 and 4.7 礔 to
ensure proper operation.
5. Soft-Start (SS)
Soft-start is programmed with a capacitor between the
SS pin and AGND. This is the non-inverting input of the
transconductance (g
M
) error amplifier.
At startup, the soft-start capacitor is quickly pre-charged
to a voltage approximately 0.5 V below the voltage on
the feedback pin (FB) to minimize startup delay. Then a
5 礎(chǔ) current source takes over and charges the soft-
start capacitor slowly, ramping up the voltage reference
of the error amplifier. By ramping up the reference
slowly, the voltage regulation loop can stay closed,
actively controlling the output voltage during startup.
While the SS capacitor is charging, the output of the
error amplifier is monitored. In case the error voltage
(COMP) ever exceeds 3.5 V, indicating that the voltage
loop is close to saturation, the 5 礎(chǔ) soft-start current is
reduced. Therefore, the soft start is automatically
extended to reduce the current needed to charge the
output capacitor, reducing the output power during
startup. This mechanism is integrated to prevent the
voltage loop from saturation. The charge current of the
soft-start capacitor can be reduced from the initial 5 礎(chǔ)
to as low as 0.5 礎(chǔ) minimum.
In addition to modulating the soft-start current into the
SS capacitor, the SS pin is clamped 0.2 V above the FB
pin. This is useful in preventing the SS capacitor from
running away from the FB pin and defeating the closed-
loop soft-start. During the zero crossing of the input
source waveform, the input power is almost zero and
the output voltage can not be raised. Therefore the FB
voltage stays flat or even decays while the SS voltage
keeps rising. This is a problem if closed-loop soft-start
should be maintained. By clamping the SS voltage to
the FB pin, this problem can be mitigated.
Furthermore, during brownout condition, the output
voltage of the converter might fall, which is reflected at
the FB pin. When FB voltage goes 0.5 V below the
voltage on the SS pin, it starts discharging the soft-start
capacitor. The soft-start capacitor remains 0.5 V above
the FB voltage. When the brownout condition is over,
the converter returns to normal operation gracefully,
following the slow ramp up of the soft-start capacitor at
the non-inverting input of the error amplifier.
Figure 19. Soft-Start Programming
6. Error Amplifier Compensation (COMP)
COMP pin is the output of the error amplifier. The
voltage loop is compensated by a combination of R
S
and C
S
to AGND at this pin. The control range of the
error amplifier is between 0.195 V and 4.3 V. When the
COMP voltage is below about 0.195 V, the PWM circuit
skips pulses. Above 4.3 V, the maximum on-time limit
terminates the conduction of the boost switches.
Due to the input-voltage feedforward, the output of the
error amplifier is proportional to the input power of the
converter, independent of the input voltage. In addition,
also due to the input-voltage feedforward, the maximum
power capability of the converter and the loop gain is
independent of the input voltage. The controllers phase-
management circuit monitors the error amplifier output
and switches to single-phase operation when the COMP
voltage falls below 0.73 V and returns to two-phase
operation when the error voltage exceeds 0.93 V. These
thresholds correspond to about 13% and 18% of the
maximum power capability of the design.
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| FAN9612 | 制造商:Fairchild 功能描述:INTERLEAVED PFC IC |
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| FAN9612MX | 功能描述:功率因數(shù)校正 IC Interleaved Dual BCM PFC Controller RoHS:否 制造商:Fairchild Semiconductor 開關(guān)頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
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