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| 型號： | FAN5019MTCX_NL |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | LEAD FREE, TSSOP-28 |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 781K |
| 代理商： | FAN5019MTCX_NL |
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PRODUCT SPECIFICATION
FAN5019
REV. 1.0.7 1/5/04
17
After the limit is reached, the 3V pull-up on the DELAY pin
is disconnected, and the external delay capacitor is dis-
charged through the external resistor. A comparator monitors
the DELAY voltage and shuts off the controller when the
voltage drops below 1.8V. The current limit latch off delay
time is therefore set by the RC time constant discharging
from 3V to 1.8V. The application section discusses the
selection of CDLY and RDLY.
Because the controller continues to cycle the phases during
the latch-off delay time, if the short is removed before the
1.8V threshold is reached, the controller will return to nor-
mal operation. The recovery characteristic depends on the
state of PWRGD. If the output voltage is within the PWRGD
window, the controller resumes normal operation. However,
if short circuit has caused the output voltage to drop below
the PWRGD threshold, then a soft-start cycle is initiated.
The latch-off function can be reset by either cycling VCC to
the FAN5019, or by cycling the Enable pin low for a short
time. To disable the short circuit latch off function, the
external resistor to ground should be left open, and a 1M
resistor should be connected from VCC to the DELAY pin.
This prevents the DELAY capacitor from discharging, so the
1.8V threshold is never reached. The resistor will have an
impact on the soft-start time because the current through it
will add to the internal 20A current source.
During start-up when the output voltage is below 200mV, a
secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit controls the internal COMP
voltage to the PWM comparators to 2V. This will limit the
voltage drop across the low side MOSFETs through the
current balance circuitry.
There is also an inherent per phase current limit that will pro-
tect individual phases in the case where one or more phases
may stop functioning because of a faulty component. This
limit is based on the maximum normal-mode COMP voltage.
Dynamic VID
The FAN5019 incorporates the ability to dynamically
change the VID input while the controller is running. This
allows the output voltage to change while the supply is run-
ning and supplying current to the load. This is commonly
referred to as VID-on-the-y (OTF). A VID-OTF can occur
under either light load or heavy load conditions. The proces-
sor signals the controller by changing the VID inputs in mul-
tiple steps from the start code to the nish code. This change
can be either positive or negative.
When a VID input changes state, the FAN5019 detects the
change and ignores the DAC inputs for a minimum of 400ns.
This time is to prevent a false code due to logic skew while
the six VID inputs are changing. Additionally, the rst VID
change initiates the PWRGD and CROWBAR blanking
functions for a minimum of 250s to prevent a false
PWRGD or CROWBAR event. Each VID change will reset
the internal timer. Figure 4 shows the VID on-the-y perfor-
mance when the output voltage is stepping up and the output
current is switching between minimum and maximum values
which is the worst-case situation.
Figure 4. VID On-the-Fly Waveforms, Circuit of Figure 5,
VID Change = 5mV, 5s, 50 steps, IOUT Change = 5A to 65A
Figure 2. Start-Up Waveforms
Figure 3. Overcurent Latch Off Waveform
Circuit of Figure 5
Channel 1 – Vout, Channel 2 – Vcc
Channel 1 – Vcc, Channel 2 – Vout
Channel 3 – OD, Channel 4 – Delay pin
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