
FAN5019
PRODUCT SPECIFICATION
26
REV. 1.0.7 1/5/04
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10. Measure the output ripple at no-load and full-load with
scope and make sure it is within spec.
AC Loadline Setting
11. Remove DC load from circuit and hook up dynamic
load.
12. Hook up scope to output voltage and set to DC coupling
with a time scale at 100s/div.
13. Set dynamic load for a transient step of about 40A at
1kHz with 50% duty cycle.
14. Measure output waveform (may have to use DC offset
on scope to see waveform). Try to use vertical scale of
100 mV/div or ner.
15. You will see a waveform that looks something like
Figure 8. Use the horizontal cursors to measure VACDRP
and VDCDRP as shown.
DO NOT MEASURE THE UNDERSHOOT OR OVER-
SHOOT THAT HAPPENS IMMEDIATELY AFTER THE
STEP.
Figure 8. AC Loadline Waveform
16. If the VACDRP and VDCDRP are different by more than a
couple of millivolts, use Equation 38 to adjust CCS. You
may need to parallel different values to get the right one
since there are limited standard capacitor values avail-
able (it is a good idea to have locations for two capaci-
tors in the layout for this).
17. Repeat Steps 11 to 13 and repeat adjustments if
necessary. Once complete, do not change CCS for the
rest of the procedure.
18. Set dynamic load step to maximum step size (do not use
a step size larger than needed) and verify that the output
waveform is square (which means VACDRP and
VDCDRP are equal). NOTE: MAKE SURE LOAD
STEP SLEW RATE AND TURN-ON ARE SET FOR A
SLEW RATE OF ~150–250A/s (for example, a load
step of 50A should take 200ns–300ns) WITH NO
OVERSHOOT. Some dynamic loads will have an
excessive turn-on overshoot if a minimum current is not
set properly (this is an issue if using a VTT tool).
Initial Transient Setting
19. With dynamic load still set at maximum step size,
expand scope time scale to see 2s/div to 5s/div. You
will see a waveform that may have two overshoots and
one minor undershoot (see Figure 9). Here, VDROOP is
the nal desired value.
Figure 9. Transient Setting Waveform
20. If both overshoots are larger than desired, try making the
following adjustments in this order. (NOTE: If these
adjustments do not change the response, you are limited
by the output decoupling.) Check the output response
each time you make a change as well as the switching
nodes (to make sure it is still stable).
a. Make ramp resistor larger by 25% (RRAMP).
b. For VTRAN1, increase CB or increase switching fre-
quency.
c. For VTRAN2, increase RA and decrease CA by 25%.
21. For load release (see Figure 10), if VTRANREL is larger
than VTRAN1 (see Figure 9), you do not have enough
output capacitance. You will either need more capaci-
tance or to make the inductor values smaller (if you
change inductors, you need to start the design over using
the spreadsheet and this tuning procedure).
DCDRP
ACDRP
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