參數(shù)資料
型號(hào)： F25L004A-50PG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類(lèi)： PROM
英文描述： 4 Mbit Uniform Sector, Serial Flash Memory
中文描述： 512K X 8 FLASH 3V PROM, PDSO8
封裝： 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁(yè)數(shù)： 9/32頁(yè)
文件大小： 393K
代理商： F25L004A-50PG
ES MT
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L004A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming,
Sector-Erase,
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE . Inputs will be accepted on the rising edge of
F25L004A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
9/32
Publication Date
:
Apr. 2007
Block-Erase,
or
Chip-Erase
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first
TABLE 5: DEVICE OPERATION
INSTRUCTIONS
Bus Cycle
3
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
2
4
5
6
Cycle Type/
Operation
1,2
Max
Freq
S
IN
03H
0BH
20H
D8H
60H
C7H
02H
S
OUT
Hi-Z A
23
-A
16
Hi-Z A
23
-A
16
Hi-Z A
23
-A
16
Hi-Z A
23
-A
16
S
IN
S
OUT
Hi-Z A
15
-A
8
Hi-Z A
15
-A
8
Hi-Z A
15
-A
8
Hi-Z A
15
-A
8
S
IN
S
IN
S
OUT
S
IN
S
OUT
A
7
-A
0
Hi-Z
A
7
-A
0
Hi-Z
A
7
-A
0
Hi-Z
A
7
-A
0
Hi-Z
S
IN
S
OUT
X
D
OUT
-
-
Read
High-Speed-Read
Sector-Erase
4,5
(4K Byte)
Block-Erase (64K Byte)
Chip-Erase
6
Byte-Program
5
Auto-Address-Increment-word
programming (AAI)
Read-Status-Register
(
RDSR
)
Enable-Write-Status-Register
(
EWSR
)
8
Write-Status-Register
(
WRSR
)
Write-Enable (
WREN
)
11
33
MHz
X
X
-
-
D
OUT
X
-
-
-
-
Hi-Z
-
-
-
-
-
-
-
-
-
-
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z
A
7
-A
0
Hi-Z D
IN
Hi-Z
-
-
ADH
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z
A
7
-A
0
Hi-Z D
IN
0 Hi-Z D
IN
1 Hi-Z
05H
Hi-Z
X
D
OUT
-
Note
7
-
Note
7
-
Note
7
-
-
50H
Hi-Z
-
-
-
-
-
-
-
-
-
-
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
-
-
06H
Hi-Z
-
-
-
-
-
-
-
-
-
-
Write-Disable (
WRDI
)
Read-Electronic-Signature
(
RES
)
04H
Hi-Z
-
-
-
-
-
-
-
-
-
-
ABH
Hi-Z
X
12H
-
-
-
-
-
-
-
-
20H(Top)
21H(Bottom)
Jedec-Read-ID (
JEDEC-ID
)
10
9FH
Hi-Z
X
8CH
X
X
13H
-
-
-
-
90H
(A0=0)
90H
(A0=1)
8CH
12H
12H
8CH
Read-ID (
RDID
)
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z
A
7
-A
0
Hi-Z
X
X
Enable SO to output RY/BY#
Status during AAI (
EBSY
)
Disable SO to output RY/BY#
Status during AAI (
DBSY
)
70H
Hi-Z
-
-
-
-
-
-
-
-
50
MHz
100
MHz
80H
Hi-Z
-
-
-
-
-
-
-
-
1. Operation: S
IN
= Serial In, S
OUT
= Serial Out
2. X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be V
IL
or V
IH
5. Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type and second byte 21H as
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