參數(shù)資料
型號(hào): F25L004A-50PG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: PROM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 512K X 8 FLASH 3V PROM, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁(yè)數(shù): 10/32頁(yè)
文件大?。?/td> 393K
代理商: F25L004A-50PG
ES MT
bottom memory type ; third byte 13H as memory capacity.
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
F25L004A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
10/32
Publication Date
:
Apr. 2007
(wrap-around) of the address space, i.e. for 4Mbit density, once
the data from address location 7FFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A
23
-A
0
]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2 : READ SEQUENCE
CE
SCK
SI
1 2 3 4 5 6 7 8
15 16
2324
31 32
39 40
4748
55 56
63 64
70
N+4
D
OUT
N+3
D
OUT
N+2
D
OUT
N+1
D
OUT
N
D
OUT
MSB
MSB
MSB
HIGH IMPENANCE
SO
03
MODE3
MODE1
ADD.
ADD.
ADD.
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