參數(shù)資料
型號: F25L004A-50PG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: PROM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 512K X 8 FLASH 3V PROM, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁數(shù): 11/32頁
文件大?。?/td> 393K
代理商: F25L004A-50PG
ES MT
Fast-Read (50 MHz ; 100 MHz)
The High-Speed-Read instruction supporting up to 100 MHz is
initiated by executing an 8-bit command, 0BH, followed by
address bits [A
23
-A
0
] and a dummy byte. CE must remain active
low for the duration of the High-Speed-Read cycle. See Figure 3
for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from the
specified address location. The data output stream is continuous
F25L004A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
11/32
Publication Date
:
Apr. 2007
through all addresses until terminated by a low to high transition
on CE . The internal address pointer will automatically increment
until the highest memory address is reached. Once the highest
memory address is reached, the address pointer will
automatically increment to the beginning (wrap-around) of the
address space, i.e. for 4Mbit density, once the data from address
location 7FFFFH has been read, the next output will be from
address location 000000H.
Figure 3 : HIGH-SPEED-READ SEQUENCE
CE
SCK
SI
0 1 2 3 4 5 6 7 8
1516
2324
3132
39 40
4748
5556
6364
80
N+4
D
OUT
N+3
D
OUT
N+2
D
OUT
N+1
D
OUT
N
D
OUT
MSB
MSB
MSB
HIGH IMPENANCE
SO
0B
ADD.
ADD.
ADD.
MODE3
MODE0
7172
X
Note : X =Dummy Byte: 8 Clocks Input Dummy (V
IL
or V
IH
)
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參數(shù)描述
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