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| 型號： | EVAL-CN0217-EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR CN0217 |
| 設(shè)計資源： | CN-0217 Circuit Eval Board |
| 標準包裝： | 1 |
| 系列： | Circuits from the Lab™ |
| 主要目的： | 阻抗轉(zhuǎn)換器 |
| 已用 IC / 零件： | AD5933，AD5934，AD8606 |
| 主要屬性： | 網(wǎng)絡(luò)分析器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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Data Sheet
AD5933
Rev. E | Page 15 of 40
FREQUENCY SWEEP COMMAND SEQUENCE
The following sequence must be followed to implement a
frequency sweep:
1. Enter standby mode. Prior to issuing a start frequency sweep
command, the device must be placed in a standby mode by
issuing an enter standby mode command to the control
register (Register Address 0x80 and Register Address 0x81).
In this mode, the VOUT and VIN pins are connected
internally to ground so there is no dc bias across the external
impedance or between the impedance and ground.
2. Enter initialize mode. In general, high Q complex circuits
require a long time to reach steady state. To facilitate the
measurement of such impedances, this mode allows the user
full control of the settling time requirement before entering
start frequency sweep mode where the impedance
measurement takes place.
An initialize with a start frequency command to the control
register enters initialize mode. In this mode the impedance
is excited with the programmed start frequency, but no meas-
urement takes place. The user times out the required settling
time before issuing a start frequency sweep command to the
control register to enter the start frequency sweep mode.
3. Enter start frequency sweep mode. The user enters this mode
by issuing a start frequency sweep command to the control
register. In this mode, the ADC starts measuring after the
programmed number of settling time cycles has elapsed. The
user can program an integer number of output frequency
cycles (settling time cycles) to Register Address 0x8A and
Register Address 0x8B before beginning the measurement
at each frequency point (see Figure 28).
The DDS output signal is passed through a programmable gain
stage to generate the four ranges of peak-to-peak output excitation
signals listed in Table 5. The peak-to-peak output excitation volt-
age is selected by setting Bit D10 and Bit D9 in the control register
Address 0X81) section) and is made available at the VOUT pin.
RECEIVE STAGE
The receive stage comprises a current-to-voltage amplifier,
followed by a programmable gain amplifier (PGA), antialiasing
filter, and ADC. The receive stage schematic is shown in
Figure 20. The unknown impedance is connected between the
VOUT and VIN pins. The first stage current-to-voltage amplifier
configuration means that a voltage present at the VIN pin is a
virtual ground with a dc value set at VDD/2. The signal current
that is developed across the unknown impedance flows into the
VIN pin and develops a voltage signal at the output of the current-
to-voltage converter. The gain of the current-to voltage amplifier
is determined by a user-selectable feedback resistor connected
between Pin 4 (RFB) and Pin 5 (VIN). It is important for the user
to choose a feedback resistance value that, in conjunction with the
selected gain of the PGA stage, maintains the signal within the
linear range of the ADC (0 V to VDD).
The PGA allows the user to gain the output of the current-to-
voltage amplifier by a factor of 5 or 1, depending upon the status
of Bit D8 in the control register (see the Register Map section,
Register Address 0x80). The signal is then low-pass filtered and
presented to the input of the 12-bit, 1 MSPS ADC.
5 × R
R
C
VIN
VDD/2
RFB
ADC
LPF
05324-
020
Figure 20. Receive Stage
The digital data from the ADC is passed directly to the DSP core
of the AD5933, which performs a DFT on the sampled data.
DFT OPERATION
A DFT is calculated for each frequency point in the sweep. The
AD5933 DFT algorithm is represented by
∑
=
=
1023
0
)))
sin(
)
)(cos(
(
)
(
n
j
n
x
f
X
where:
X(f) is the power in the signal at the Frequency Point f.
x(n) is the ADC output.
cos(n) and sin(n) are the sampled test vectors provided by the
DDS core at the Frequency Point f.
The multiplication is accumulated over 1024 samples for each
frequency point. The result is stored in two, 16-bit registers
representing the real and imaginary components of the result.
The data is stored in twos complement format.
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