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| 型號： | EVAL-CN0217-EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR CN0217 |
| 設(shè)計資源： | CN-0217 Circuit Eval Board |
| 標準包裝： | 1 |
| 系列： | Circuits from the Lab™ |
| 主要目的： | 阻抗轉(zhuǎn)換器 |
| 已用 IC / 零件： | AD5933，AD5934，AD8606 |
| 主要屬性： | 網(wǎng)絡(luò)分析器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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Data Sheet
AD5933
Rev. E | Page 27 of 40
SERIAL BUS INTERFACE
Control of the AD5933 is carried out via the I2C-compliant
serial interface protocol. The AD5933 is connected to this bus
as a slave device under the control of a master device. The
AD5933 has a 7-bit serial bus slave address. When the device is
powered up, it has a default serial bus address, 0001101 (0x0D).
GENERAL I2C TIMING
Figure 29 shows the timing diagram for general read and write
operations using the I2C-compliant interface.
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line
(SDA), while the serial clock line (SCL) remains high. This
indicates that a data stream follows. The slave responds to the
start condition and shifts in the next 8 bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit that determines
the direction of the data transfer—that is, whether data is
written to or read from the slave device (0 = write, 1 = read).
The slave responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and holding it low during the high period of this clock
pulse. All other devices on the bus remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is 0, then the master writes to the slave device.
If the R/W bit is 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit, which
can be from the master or slave device. Data transitions on the
data line must occur during the low period of the clock signal
and remain stable during the high period, because a low-to-
high transition when the clock is high may be interpreted as a
stop signal. If the operation is a write operation, the first data
byte after the slave address is a command byte. This tells the
slave device what to expect next. It may be an instruction telling
the slave device to expect a block write, or it may be a register
address that tells the slave where subsequent data is to be
written. Because data can flow in only one direction as defined
by the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it is sometimes necessary to perform a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge. The
master then takes the data line low during the low period
before the 10th clock pulse, then high during the 10th clock
pulse to assert a stop condition.
0
1
0
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START CONDITION
BY MASTER
ACKNOWLEDGE BY
AD5933
SLAVE ADDRESS BYTE
ACKNOWLEDGE BY
MASTER/SLAVE
SCL
SDA
REGISTER ADDRESS
05324-
035
Figure 29. Timing Diagram
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