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| 型號： | EVAL-CN0217-EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/40頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR CN0217 |
| 設計資源： | CN-0217 Circuit Eval Board |
| 標準包裝： | 1 |
| 系列： | Circuits from the Lab™ |
| 主要目的： | 阻抗轉換器 |
| 已用 IC / 零件： | AD5933，AD5934，AD8606 |
| 主要屬性： | 網(wǎng)絡分析器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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AD5933
Data Sheet
Rev. E | Page 18 of 40
TWO-POINT CALIBRATION
Alternatively, it is possible to minimize this error by assuming
that the frequency variation is linear and adjusting the gain
factor with a two-point calibration. Figure 23 shows an
impedance profile based on a two-point gain factor calculation.
101.5
98.5
54
66
FREQUENCY (kHz)
IMPED
A
N
C
E
(k
)
101.0
100.5
100.0
99.5
99.0
56
58
60
62
64
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
TA = 25°C
MEASURED CALIBRATION IMPEDANCE = 100k
05324-
023
Figure 23. Impedance Profile Using a Two-Point Gain Factor Calculation
TWO-POINT GAIN FACTOR CALCULATION
This is an example of a two-point gain factor calculation
assuming the following:
Output excitation voltage = 2 V (p-p)
Calibration impedance value, ZUNKNOWN = 100.0 k
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 k
Calibration frequencies = 55 kHz and 65 kHz
Typical values of the gain factor calculated at the two calibration
frequencies read
Gain factor calculated at 55 kHz is 1.031224E-09
Gain factor calculated at 65 kHz is 1.035682E-09
Difference in gain factor (GF) is 1.035682E-09
1.031224E-09 = 4.458000E-12
Frequency span of sweep (F) = 10 kHz
Therefore, the gain factor required at 60 kHz is given by
9
-
10
031224
.
1
kHz
5
kHz
10
12
-
E
458000
.
4
×
+
×
The required gain factor is 1.033453E-9.
The impedance is calculated as previously described.
GAIN FACTOR SETUP CONFIGURATION
When calculating the gain factor, it is important that the receive
stage operate in its linear region. This requires careful selection
of the excitation signal range, current-to-voltage gain resistor,
and PGA gain.
VIN
VDD/2
RFB
ADC
LPF
ZUNKNOWN
VOUT
CURRENT-TO-VOLTAGE
GAIN SETTING RESISTOR
PGA
(×1 OR ×5)
05324-
024
Figure 24. System Voltage Gain
The gain through the system shown in Figure 24 is given by
Gain
PGA
Z
sistor
Setting
Gain
Range
Voltage
Excitation
Ouput
UNKNOWN
×
Re
For this example, assume the following system settings:
VDD = 3.3 V
Gain setting resistor = 200 k
ZUNKNOWN = 200 k
PGA setting = ×1
The peak-to-peak voltage presented to the ADC input is
2 V p-p. However, if a PGA gain of ×5 was chose, the voltage
would saturate the ADC.
GAIN FACTOR RECALCULATION
The gain factor must be recalculated for a change in any of the
following parameters:
Current-to-voltage gain setting resistor
Output excitation voltage
PGA gain
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