參數(shù)資料
型號(hào)： EVAL-ADUC7028QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 26/104頁
文件大?。?/td> 0K
描述： KIT DEV ADUC7028 QUICK START
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7028
所含物品： 評(píng)估板、電源、纜線、軟件和說明文檔
產(chǎn)品目錄頁面： 739 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： ADUC7028BBCZ62-RL-ND - IC MCU FLASH 62K 12BIT
ADUC7028BBCZ62-ND - IC MCU FLASH 62K 12BIT
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 28 of 104
ADuC7026/ADuC7027
04955-
069
1
ADC4
2
ADC5
3
ADC6
4
ADC7
5
ADC8
6
ADC9
7
ADC10
8
GNDREF
9
ADCNEG
10
DAC0/ADC12
11
DAC1/ADC13
12
DAC2/ADC14
13
DAC3/ADC15
14
TMS
15
TDI
16
P0.1/PWM2H/BLE
17
P2.3/AE
18
P4.6/AD14/PLAO[14]
19
P4.7/AD15/PLAO[15]
20
BM/P0.0/CMPOUT/PLAI[7]/MS0
60
P1.2/SPM2/PLAI[2]
59
P1.3/SPM3/PLAI[3]
58
P1.4/SPM4/PLAI[4]/IRQ2
57
P1.5/SPM5/PLAI[5]/IRQ3
56
P4.1/AD9/PLAO[9]
55
P4.0/AD8/PLAO[8]
54
IOVDD
53
IOGND
52
P1.6/SPM6/PLAI[6]
51
P1.7/SPM7/PLAO[0]
50
P2.2/RS/PWM0L/PLAO[7]
49
P2.1/WS/PWM0H/PLAO[6]
48
P2.7/PWM1L/MS3
47
P3.7/AD7/PWMSYNC/PLAI[15]
46
P3.6/AD6/PWMTRIP/PLAI[14]
45
XCLKI
44
XCLKO
43
P0.7/ECLK/XCLK/SPM8/PLAO[4]
42
P2.0/SPM9/PLAO[5]/CONVSTART
41
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2
21
P
0
.6
/T1
/M
R
S
T/P
LA
O[
3
]
22
T
CK
23
T
DO
24
P0
.2
/PW
M2
L
/BHE
25
IOGN
D
26
IOV
DD
27
LV
DD
28
DG
ND
29
P
3.
0/
AD0/
P
W
M
0
H
/P
LA
I[
8
]
30
P
3.
1/
AD1/
P
W
M
0
L
/P
LA
I[
9
]
31
P
3.
2/
AD2/
P
W
M
1
H
/P
L
AI
[10]
32
P
3.
3/
AD3/
P
W
M
1
L
/P
L
AI
[11]
33
P2
.4
/PW
M0
H
/MS0
34
P
0.
3/
T
RS
T
/A16/
ADC
BUS
Y
35
P2
.5
/PW
M0
L
/MS1
36
P2
.6
/PW
M1
H
/MS2
37
RS
T
38
P
3.
4/
AD4/
P
W
M
2
H
/P
L
AI
[12]
39
P
3.
5/
AD5/
P
W
M
2
L
/P
L
AI
[13]
40
IR
Q0
/P
0
.4
/P
WM
T
RI
P
/PL
A
O
[1
]/
MS1
80
ADC3/
CM
P
1
79
ADC2/
CM
P
0
78
ADC1
77
ADC0
76
ADC11
75
DACV
DD
74
AV
DD
73
AV
DD
72
AG
ND
71
AG
ND
70
DACG
ND
69
DAC
RE
F
68
V
RE
F
67
RE
F
G
ND
66
P
4.
5/
AD13/
P
L
AO
[13]
65
P
4.
4/
AD12/
P
L
AO
[12]
64
P
4.
3/
AD11/
P
L
AO
[11]
63
P
4.
2/
AD10/
P
L
AO
[10]
62
P
1
.0
/T1
/S
P
M
0
/P
LA
I[
0
]
61
P1
.1
/SPM1
/PL
A
I[1
]
TOP VIEW
(Not to Scale)
ADuC7026/
ADuC7027
PIN 1
INDICATOR
Figure 25. 80-Lead LQFP Pin Configuration (ADuC7026/ADuC7027)
Table 13. Pin Function Descriptions (ADuC7026/ADuC7027)
Pin No.
Mnemonic
Description
1
ADC4
Single-Ended or Differential Analog Input 4.
2
ADC5
Single-Ended or Differential Analog Input 5.
3
ADC6
Single-Ended or Differential Analog Input 6.
4
ADC7
Single-Ended or Differential Analog Input 7.
5
ADC8
Single-Ended or Differential Analog Input 8.
6
ADC9
Single-Ended or Differential Analog Input 9.
7
ADC10
Single-Ended or Differential Analog Input 10.
8
GNDREF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
9
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
10
DAC0/ADC12
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7027.
11
DAC1/ADC13
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7027.
12
DAC2/ADC14
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not
present on the ADuC7027.
13
DAC3/ADC15
DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not
present on the ADuC7027.
14
TMS
JTAG Test Port Input, Test Mode Select. Debug and download access.
15
TDI
JTAG Test Port Input, Test Data In. Debug and download access.
16
P0.1/PWM2H/BLE
General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
Byte Low Enable.
17
P2.3/AE
General-Purpose Input and Output Port 2.3/External Memory Access Enable.
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