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參數(shù)資料
| 型號(hào)： | EVAL-ADF4118EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 17/28頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4118 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4118 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 1.96GHz WCDMA 圖形用戶界面 |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | ADF4118BRUZ-RL7TR-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP ADF4118BRUZ-RL-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP ADF4118BRUZ-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4118BRU-REEL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4118BRU-ND - IC SYNTH PLL RF 3.0GHZ 16-TSSOP |
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ADF4116/ADF4117/ADF4118
Rev. D | Page 24 of 28
INTERFACING
The ADF411x family has a simple SPI-compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE (latch enable) goes high, the 24 bits that
are clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 μs. This is more than adequate for
systems that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 38 shows the interface between the ADF411x family and
the ADuC812 MicroConverter. Since the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF411x family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
SCLOCK
MOSI
I/O PORTS
ADuC812
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4116/
ADF4117/
ADF4118
0
039
2-
0
38
Figure 38. ADuC812 to ADF411x family Interface
On first applying power to the ADF411x family, it requires three
writes (one each to the R counter latch, the N counter latch, and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed is 166 kHz.
ADSP-21xx Interface
Figure 39 shows the interface between the ADF411x family and
the ADSP-21xx digital signal processor. The ADF411x family
needs a 21-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
SCLK
DT
I/O FLAGS
ADSP-21xx
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4116/
ADF4117/
ADF4118
TFS
00
39
2-
03
9
Figure 39. ADSP-21xx to ADF411x family Interface
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 21-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4118EBZ11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| EVAL-ADF411XEB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF411XEBZ1 | 功能描述:BOARD EVAL FOR ADF411X NO CHIP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF411XEBZ11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| EVAL-ADF4150EB1Z | 制造商:Analog Devices 功能描述:EVAL BOARD PLL SYNTH/VCO ADF4150 制造商:Analog Devices 功能描述:ADF4150, PLL SYNTHESIZER, EVAL BOARD 制造商:Analog Devices 功能描述:ADF4150, PLL SYNTHESIZER, EVAL BOARD; Silicon Manufacturer:Analog Devices; Kit Application Type:Clock & Timing; Application Sub Type:VCO; Features:Fractional-N Synthesizer and Integer-N Synthesizer, 3-wire Serial Interface; SVHC:No ;RoHS Compliant: Yes |
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