參數(shù)資料
型號: EVAL-ADF4118EBZ1
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADF4118
標準包裝: 1
主要目的: 計時,頻率合成器
嵌入式:
已用 IC / 零件: ADF4118
主要屬性: 單路整數(shù)-N PLL
次要屬性: 1.96GHz WCDMA 圖形用戶界面
已供物品: 板,纜線,CD
相關(guān)產(chǎn)品: ADF4118BRUZ-RL7TR-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP
ADF4118BRUZ-RL-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP
ADF4118BRUZ-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP
ADF4118BRU-REEL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP
ADF4118BRU-ND - IC SYNTH PLL RF 3.0GHZ 16-TSSOP
ADF4116/ADF4117/ADF4118
Rev. D | Page 18 of 28
M3
0
1
M2
0
1
0
1
M1
0
1
0
1
0
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
AVDD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N CHANNEL OPEN DRAIN)
SERIAL DATA OUTPUT
(INVERSE POLARITY OF
SERIAL DATA INPUT)
DGND
TC4
0
1
TC3
0
1
0
1
TC2
0
1
0
1
0
1
0
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
F1
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
F2
0
1
NEGATIVE
POSITIVE
F3
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
0
1
CE PIN PD2 PD1
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
X
0
1
X
0
1
F6
X
0
1
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
F4
0
1
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB10
PD2
TC4
TC3
TC2
TC1
F6
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1)
C1 (1)
CONTROL
BITS
MUXOUT
CONTROL
PO
W
E
R
-
DO
W
N
2
PO
W
E
R
-
DO
W
N
1
FA
S
T
L
O
C
K
E
N
ABL
E
CP
T
HRE
E
-
ST
A
T
E
FA
S
T
L
O
C
K
MO
D
E
TIMER COUNTER
CONTROL
RESERVED
R
E
SE
R
V
ED
X
R
E
SE
R
V
ED
XX
X
P
HAS
E
DE
T
E
C
T
O
R
P
O
L
ARI
TY
PHASE DETECTOR
POLARITY
00
39
2-
0
34
CO
UNT
E
R
ESE
T
Figure 34. Initialization Latch Map
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