參數(shù)資料
型號(hào)： EVAL-AD7933CB
廠商： Analog Devices, Inc.
元件分類： ADC
英文描述： 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
中文描述： 4通道，1.5 MSPS的12位和10位并行ADC的一個(gè)序列
文件頁(yè)數(shù)： 26/32頁(yè)
文件大小： 1253K
代理商： EVAL-AD7933CB
AD7933/AD7934
Preliminary Technical Data
Writing Data to the AD7933/AD7934
With W/B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7933/AD7934. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7933/AD7934 should be
provided on the DB0 to DB11 inputs with DB0 being the LSB of
the data-word. With W/B tied logic low, the AD7933/AD7934
requires two write operations to transfer a full 12-bit word.
DB8/HBEN assumes its HBEN function. Data written to the
AD7933/AD7934 should be provided on the DB0 to DB7
inputs. HBEN determines whether the byte written is high byte
or low byte data. The low byte of the data-word has DB0 being
the LSB of the full data-word. For the high byte write, HBEN
should be high and the data on the DB0 input should be data bit
8 of the 12 bit word.
Figure 39
AD7933/AD7934. When operated in word mode, the HBEN
input does not exist and only the one write operation is required
Figure 39. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1)
shows the write cycle timing diagram of the
to write the word of data to the device. Data should be provided
on DB0 to DB11. When operated in byte mode, the two write
cycles shown in F
are required to write the full data-
word to the AD7933/AD7934. In F
transfers the lower 8 bits of the data-word from DB0 to DB7
and the second write transfers the upper 4 bits of the data-word.
, the first write
igure 40
igure 40
Figure 40. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0)
When writing to the AD7933/AD7934, the top 4 bits in the high
byte must be 0s.
The data is latched into the device on the rising edge of WR.
The data needs to be setup a time, t
7
, before the WR rising edge
and held for a time, t
8
, after the WR rising edge. The CS and WR
signals are gated internally. CS and WR may be tied together as
the timing specification for t
4
and t
5
is 0 ns minimum (assuming
CS and RD have not already been tied together).
t
8
t
5
t
7
t
6
t
4
DATA
DB0 TO DB11
WR
CS
0
t
5
t
4
t
7
t
18
t
18
t
19
t
19
t
8
t
6
t
17
LOW BYTE
HIGH BYTE
DB0 TO DB7
HBEN/DB8
WR
CS
0
Rev. PrG | Page 26 of 32
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